• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1364-1369
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• 2005

In this paper, we have identified the mechanism of C-V hysteresis behavior often observed in pentacene organic thin-film transistors (OTFTs). The capacitance-voltage (C-V) characteristics were measured for pentacene OTFTs fabricated on glass substrates with MoW as gate/source/drain electrode and TEOS $SiO_2$ as gate insulator. The measurements were made at room temperature and elevated temperatures. From the room temperature measurements, we found that the hysteresis behavior was caused by hole injection into the gate insulator from the pentacene semiconductor for large negative gate voltages, resulting in the negative flat-band voltage shift. However electron injection was observed only at elevated temperatures

• 한국진공학회지
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• 제13권3호
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• pp.99-102
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• 2004

유기 절연층을 사용한 유기 박막 트랜지스터의 특성 향상을 위해 절연층 표면에 Ar플라즈마 처리를 하였다. 플라즈마 처리는 절연체 표면의 화학적, 물리적 특성 변화를 통해 그 후에 이어지는 활성층 성막시 분자들의 결정성을 향상시키기 위한 방법이다. 활성층으로 사용된 물질은 pentacene이며, 절연층으로 사용된 물질은 PVP(poly-vinyl-phenol)이다. Pentacene는 약 $10^{-6}$ Torr에서 0.5 $\AA$/sec의 속도로, PVP는 spin coating법에 의해 각각 성막되었다. 형성된 절연층을 일정 시간동안 H플라즈마 처리 한 후 각 소자의 전기적 특성을 측정하여 표면처리에 의한 특성 변화를 살펴보았다.

• 한국전기전자재료학회논문지
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• 제15권2호
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• pp.110-118
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• 2002

Organic thin film transitors(OTFT) are of interest for use in broad area electronic applications. And recently organic electroluminescent devices(OELD) have been intensively investigated for using in full-color flat-panel display. We have fabricated inverted-staggered structure OTFTs at lower temperature using the fused-ring polycyclic aromatic hydrocarbon pentacene as the active eletronic material and photoacryl as the organic gate insulator. The field effect mobility is 0.039∼0.17 ㎠/Vs, on-off current ratio is 10$\^$6/, and threshold voltage is -7V. And here we report the study of driving emitting, Ir(ppy)$_3$, phosphorescent OELD with all organic thin film transistor and investigated its electrical characteristics. The OELD with a structure of ITO/TPD/8% Ir(ooy)$_3$ doped in BCP/BCP/Alq$_3$/Li:Al/Al and OTFT with a structure of inverted-stagged Al(gate electrode)/photoacry(gate insulator)/pentacene(p-type organic semiconductor)/ Au(source-drain electrode) were fabricated on the ITP patterned glass substrate. The electrical characteristics are turn-on voltage of -10V, and maximum luminance of about 90 cd/㎡. Device characteristics were quite different with that of only OELD.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.35-39
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• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.93-96
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• 2004

The a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_{3}N_{4}$. Ferroelectric increases on-current, decreases threshold voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, retractive index of 1.8∼2.0 and resistivity of $10^{13}$~$10^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60∼100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8∼20 $\mu\textrm{m}$ and channel width of 80∼200 $\mu\textrm{m}$. And it shows that drain current is 3.4$\mu\textrm{A}$ at 20 gate voltage, $I_{on}$/$I_{off}$ is a ratio of $10^5$~$10^8$ and $V_{th}$ is 4∼5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $\mu\textrm{A}$ at 20 gate voltage and $V_{th}$ is 5∼6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.666-672
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• 2014

We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal $SiO_2$, a plasma-enhanced chemical vapor deposition (PECVD) $SiO_x$, a $150^{\circ}C$-deposited PEVCD $SiO_x$, and a $300^{\circ}C$-deposited PECVD $SiO_x$. Among the devices, the one with the $150^{\circ}C$-deposited PEVCD $SiO_x$ exhibits the best electrical performance including a high field-effect mobility ($=4.86cm^2/Vs$), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1220-1224
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• 2007

The effects of plasma damages to the organic thin film transistor (OTFT) during the fabrication process are investigated; metal deposition process on the organic gate insulator by plasma sputtering mainly generates the process induced damages of bottom contact structured OTFTs. For this study, various deposition methods (thermal evaporation, plasma sputtering, and neutral beam based sputtering) and metals (gold and Indium-Tin Oxide) have been tested for their damage effects onto the Poly 4-vinylphenol(PVP) layer surface as an organic gate insulator. The surface damages are estimated by measuring surface energies and grain shapes of organic semiconductor on the gate insulator. Unlike thermal evaporation and neutral beam based sputtering, conventional plasma sputtering process induces serious damages onto the organic surface as increasing surface energy, decreasing grain sizes, and degrading TFT performance.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.385-388
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• 2009

We have investigated the effect of the device structure on the performance of polycrystalline ZnO TFT and amorphous AZTO TFT with top gate and bottom gate structure. While the mobility of both TFTs showed relatively similar value in a top and bottom gate structure, bias stability was quite different depending on the device structure. Top gate TFT showed much less Vth shift under positive bias stress compared to that of bottom gate TFT. We attributed this different behavior to the defects formation on the gate insulator induced by energetic bombardment during the active layer deposition in a bottom gate TFT. We suggest the top gate oxide TFT would show more stable behavior under the Vgs bias.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.283-284
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• 2012

In this work, a special technique called dielectric filling was carried out in order to reduce sub-threshold leakage current inside double-gated n-channel MOSFET. This calibration was done by using SILVACO Atlas(TCAD), and the result showed quite a good performance compared to the conventional double-gate MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.223-229
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• 2017

This paper analyzes the effect of a dual-metal-gate structure on the electrical characteristics of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. These structures have two gate metals of different work function values (${\Phi}$), with the metal of higher ${\Phi}$ in the source-side gate, and the metal of lower ${\Phi}$ in the drain-side gate. As a result of the different ${\Phi}$ values of the gate metals in this structure, both the electric field and electron velocity in the channel become better distributed. For this reason, the transconductance, current collapse phenomenon, breakdown voltage, and radio frequency characteristics are improved. In this work, the devices were designed and analyzed using a 2D technology computer-aided design simulation tool.