• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.907-911
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• 2006

In this paper, we propose a new structure that improves the on-state voltage drop and switching speed in Insulated Gate Bipolar Transistors(IGBTs), which can be widely used in high voltage semiconductors. The proposed structure is unique in that the collector area is divided by $SiO_2$, whereas the conventional IGBT has a planar P+ collector structure. The process and device simulation results show remarkably improved on-state and switching characteristics. Also, the current and electric field distribution indicate that the segmented collector structure has increased electric field near the $SiO_2$ corner, which leads to an increase of electron current. This results in a decrease of on-state resistance and voltage drop to $30%{\sim}40%$. Also, since the area of the P+ region is decreased compared to existing structures, the hole injection decreases and leads to an increase of switching speed to 30 %. In spite of some complexity in process procedures, this structure can be manufactured with remarkably improved characteristics.

• 공업화학
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• 제26권1호
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• pp.116-119
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• 2015

전계 효과 트랜지스터(FET) 기반의 이온 또는 바이오센서에 대한 연구는 지금까지 활발하게 이루어지고 있다. 본 논문에서는 여러 가지 측정 방법 중에 FET 게이트 절연체 위의 감지막과 이온 또는 생분자의 상호작용으로 전하 분포의 변화가 일어나면 이로 인해 드레인 전류의 변화를 측정하는 방법을 기반으로, 동일한 입력 신호, 즉 동일한 이온 또는 생분자의 농도에 대해 최적의 출력 신호를 얻기 위한 방법에 대해 논의한다. 대표적인 FET 센서는 이온 감지 FET (ISFET)로 본 논문에서는 pH를 측정하는 센서를 이용하였다. ISFET는 게이트 전압 대신 기준전극 전압을 가하는데 이 기준전극 전압과 드레인 전류의 관계식을 측정하여, 가장 기울기가 큰 곳을 찾아 이를 기준으로 동작범위에서의 입력 변화에 대해 출력 신호인 포화영역에서 드레인 전류의 변화가 큰 조건을 설정해 보았다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.58-61
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• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• 한국전기전자재료학회논문지
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• 제11권6호
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.1-4
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• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

• Transactions on Electrical and Electronic Materials
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• 제8권1호
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• pp.36-40
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• 2007

Inorganic layers, such as SiOxNy and SiOx deposited using plasma sublimation method, were tested as passivation layer for organic thin-film-transistors (OTFTs). OTFTs with bottom-gate and bottom-contact structure were fabricated using pentacene as organic semiconductor and an organic gate insulator. SiOxNy layer gave little change in characteristics of OTFTs, but SiOx layer degraded the performance of OTFTs severely. Inferior barrier properties related to its lower film density, higher water vapor transmission rate (WVTR) and damage due to process environment of oxygen of SiOx film could explain these results. Polyurea and polyvinyl acetates (PVA) were tested as organic passivation layers also. PVA showed good properties as a buffer layer to reduce the damage come from the vacuum deposition process of upper passivation layers. From these results, a multilayer structure with upper SiOxNy film and lower PVA film is expected to be a superior passivation layer for OTFTs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.217-222
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• 2003

A new two-dimensional analytical model for the potential distribution and drain-induced barrier lowering (DIBL) effect of fully depleted short-channel Silicon-on-insulator (SOI)-MESFET's has been presented in this paper. The two dimensional potential distribution functions in the active layer of the device is approximated as a simple parabolic function and the two-dimensional Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. It is observed that for the SOI-MESFET's, as the gate-length is decreased below a certain limit, the bottom potential is increased and thus the channel barrier between the drain and source is reduced. The similar effect may also be observed by increasing the drain-source voltage if the device is operated in the near threshold or sub-threshold region. This is an electrostatic effect known as the drain-induced barrier lowering (DIBL) in the short-gate SOI-MESFET's. The model has been verified by comparing the results with that of the simulated one obtained by solving the 2-D Poisson's equation numerically by using the pde toolbox of the widely used software MATLAB.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.341.1-341.1
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• 2014

In the advanced material for the next generation display device, transparent amorphous oxide semiconductors (TAOS) are promising materials as a channel layer in thin film transistor (TFT). The TAOS have many advantages for large-area application compared with hydrogenated amorphous silicon TFT (a-Si:H) and organic semiconductor TFT. For the reasonable characteristics of TAOS, The a-IGZO has the excellent performances such as low temperature fabrication (R.T~), high mobility, visible region transparent, and reasonable on-off ratio. In this study, we investigated how the electric characteristics and physical properties are changed as various oxygen ratio when magnetron sputtering. we analysis a-IGZO film by AFM, EDS and I-V measurement. decreasing the oxygen ratio, the threshold voltage is shifted negatively and mobility is increasing. Through this correlation, we confirm the effect of oxygen ratio. We fabricated the bottom-gate a-IGZO TFTs. The gate insulator, SiO2 film was grown on heavily doped silicon wafer by thermal oxidation method. a-IGZO channel layer was deposited by RF magnetron sputtering. and the annealing condition is $350^{\circ}C$. Electrode were patterned Al deposition through a shadow mask(160/1000 um).

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.69-70
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• 2000

There are currently considerable interest in the applications of conjugated polymers, oligomers, and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field-effect transistors and light-emitting diodes. In this study, pentacene thin-film transistors (TFTs) were fabricated on glass substrate. Aluminums were used for gate electrodes. Silicon dioxide was deposited as a gate insulator by PECVD and patterned by reactive ion etching (R.I.E). Gold was used for the electrodes of source and drain. The active semiconductor pentacene layer was thermally evaporated in vacuum at a pressure of about $10^{-8}$ Torr and a deposition rate $0.3{\AA}/s$. The fabricated devices exhibited the field-effect mobility as large as 0.07 $cm^2/V.s$ and on/off current ratio as larger than $10^7$.