• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.223-226
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• 2003

The EKV model, a continuous model for the MOS transistor, has been adapted to both partially depleted SOI MOSFETs with grounded body (GBSOI) and dynamic threshold MOS (DTMOS) transistors. Adaptation is straightforward and helps to understand the physics of the DTMOS. Excellent agreement is found between the model and the measured characteristics of GBSOI and DTMOS devices

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.215-216
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• 2000

We fabricated the thin-film transistors using organic semiconductor, pentacene, on $SiN_x$, gate insulator. X-ray diffraction experiments were performed for the sample after heat-treatments at higher temperatures. We confirmed that we obtained "thin-film phase" from the condition used here. From the electrical measurements, we also confirmed that no charges are accumulated at the interface between organic and insulating layer, and FET characteristics of the organic FET using pentacene was discussed.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 추계종합학술대회
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• pp.800-803
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• 2002

The MONOS capacitor are fabricated to investigate the carrier trapping due to Fowler-Nordheim tunneling injection. The carrier trapping in scaled multi-dielectric(ONO) depends on the nitride and Op oxide thickness under Fowler_Nordheim tunneling injection. Carriers captured at nitride film could not escape from nitride to gate, but be captured at top oxide and nitride interface traps because of barrier height of top oxide. Therefore, it is expected that the MONOS memory devices using multi dielectric films enhance memory effect and have a long memory retention characteristic.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.159-161
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• 2007

We fabricated flexible OTFT-backplanes for the electrophoretic display(EPD). The OTFTs employed bottom contact structure on PEN substrate and used the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. Especially, we used PVA/Acryl double layers for passivation of backplane as well as for pixel dielectric layer between backplane and EPD panel. The OTFT-EPD panel worked successfully anddemonstrated to display some patterns.

• 전자공학회논문지A
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• 제30A권3호
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• pp.61-66
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• 1993

The interface properties of Fluoride/GaAs structures were investigated. It was foung that rapid thermal annealing(RTA) typically 800-850$^{\circ}C$for 1 min, was useful for improving the interface properties of that structures. The analysis by means of SIMS indicated that interdiffusion of each constitutional atom through the interface was negligible. The interfacial atom bonding model for RTA treatment was proposed. Bases on these results, inversion-type GaAs MISFET was fabricated using standard planar technologies.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2006년도 춘계학술발표대회 및 제10회 신소재 심포지엄 논문개요집
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• pp.23.2-23.2
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• 2006

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.190-193
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• 2002

The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.213-225
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• 2002

Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.445-447
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• 2016

터널링 전계효과 트랜지스터(Tunneling Field-Effect Transistor; TFET) 중에 이중 게이트 TFT(DG-TFET)와 단일 게이트 TFET(SG-TFET)의 구조에 따른 성능 비교를 조사했다. 채널 길이가 30nm 이상, 실리콘 두께 20nm이하, 게이트 절연막 두께는 작아질수록 SG-TFET와 DG-TFET subthrreshold swing과 온 전류 성능이 향상됨을 보였다. 다양한 파라미터에서 DG-TFET의 성능이 SG-TFET 성능보다 향상됨을 보인다.