• 센서학회지
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• 제15권2호
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• pp.90-96
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• 2006

We have fabricated the Pd-blck/NiCr gate MISFET-type $H_2$ sensor to detect the hydrogen in atmosphere. A differential pair-type structure was used to minimize the intrinsic voltage drift of the MISFET. The Pd-black film was deposited in the argon environment by thermal evaporation. In order to eliminate the blister formation in the surface of the hydrogen sensing gate metal, Pd-black/NiCr double metal layer was deposited on the gate insulator. The scanning electron microscopy and the auger electron spectroscopy was used to analyze their surface morphology and basic structure. The Pd-black/NiCr gate MISFET has been shown high sensitivity and stability more than Pd-planar/NiCr gate MISFET.

• 한국전기전자재료학회논문지
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• 제27권2호
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.601-608
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• 2014

In this paper, we have characterized the electrical properties related to gate leakage current in AlGaN/GaN MISHFETs with varying the thickness (0 to 10 nm) of $Al_2O_3$ gate insulator which also serves as a surface protection layer during high-temperature RTP. The sheet resistance of the unprotected TLM pattern after RTP was rapidly increased to $1323{\Omega}/{\square}$ from the value of $400{\Omega}/{\square}$ of the as-grown sample due to thermal damage during high temperature RTP. On the other hand, the sheet resistances of the TLM pattern protected with thin $Al_2O_3$ layer (when its thickness is larger than 5 nm) were slightly decreased after high-temperature RTP since the deposited $Al_2O_3$ layer effectively neutralizes the acceptor-like states on the surface of AlGaN layer which in turn increases the 2DEG density. AlGaN/GaN MISHFET with 8 nm-thick $Al_2O_3$ gate insulator exhibited extremely low gate leakage current of $10^{-9}A/mm$, which led to superior device performances such as a very low subthreshold swing (SS) of 80 mV/dec and high $I_{on}/I_{off}$ ratio of ${\sim}10^{10}$. The PF emission and FN tunneling models were used to characterize the gate leakage currents of the devices. The device with 5 nm-thick $Al_2O_3$ layer exhibited both PF emission and FN tunneling at relatively lower gate voltages compared to that with 8 nm-thick $Al_2O_3$ layer due to thinner $Al_2O_3$ layer, as expected. The device with 10 nm-thick $Al_2O_3$ layer, however, showed very high gate leakage current of $5.5{\times}10^{-4}A/mm$ due to poly-crystallization of the $Al_2O_3$ layer during the high-temperature RTP, which led to very poor performances.

• 센서학회지
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• 제9권2호
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• pp.113-119
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• 2000

정류수 내 수소 가스를 감지할 수 있는 Pd 박막을 가진 Pd/Pt 게이트 MISFET 수소센서를 제조하였다. 감지게이트 MISFET와 기준 게이트 MISFET의 차동형 센서로 제작하여 MOSFET 고유의 드리프트를 최소화하였다. 수소유입으로 인한 드리프트는 $Si_3N_4/SiO_2$의 이중 게이트 절연막으로 줄였고, 수소에 의한 Pd의 격자 팽창에 의해 생기는 블리스터는 Pt을 넣어서 제거하였다. Pd 박막을 수소 여과기로 사용한 Pd/Pt 게이트 MISFET 센서로 측정한 결과 $0{\sim}500\;ppm$ 사이에서 선형적인 출력 특성을 얻을 수 있었다. 30 일간 $50^{\circ}C$의 정류수 속에서 장기안정도를 측정하였다. 전체적으로 감지 FET의 게이트 전압은 35 mV 상승하였고, 기준 FET는 48 mV 상승하여 안정한 특성을 나타내었다.

• 한국인터넷방송통신학회논문지
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• 제10권6호
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• pp.243-249
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• 2010

본 논문에서는 대칭형 이중 게이트 MOSFET의 회로해석에 대한 등가모델을 제시하고자 해석적 모델을 연구하였다. 본 연구의 해석적 모델에 사용된 방법은 2차원 포아송 방정식의 해를 가정하여 표면 전위 관계식을 유도하여 실리콘 몸체 내의 전위분포를 풀어 드레인 전압 변화에 대한 문턱전압 관계식을 도출하였다. 단채널 및 장채널 실리콘 채널에서 모두 해석이 가능한 해석적 모델을 적용 가능하도록 하기 위해 MOSFET의 채널 길이에 따른 제한된 지수함수를 적용함으로써 수백 나노미터까지 해석이 가능한 대칭형 이중 게이트 MOSFET 해석적 모델을 연구하였다.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2002년도 춘계 학술발표강연 및 논문개요집
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• pp.47-47
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• 2002

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제36회 동계학술대회 초록집
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• pp.271.1-271.1
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• 2009

• 한국진공학회:학술대회논문집
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• 한국진공학회 2008년도 제35회 하계학술대회 초록집
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• pp.281-281
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• 2008