• Journal of the Korea Society of Computer and Information
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• v.6 no.2
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• pp.58-64
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• 2001

The quantity of container transportation of the world harbors is constantly increasing by 8.8％ per year until 2011. present port facilities will not satisfy it. So facility expansion is necessary. Because the processing cost in the harbor becomes to 30％ of total transportation expense, major ports in the world are making an effort in the automation facilities to solve the problems of higher labor costs and insufficient labor and to maximize the efficiency of the work and use of the land. Especially, the automation of the gate, which is the place of cargo's appearance and disappearance, the node which creates the information. is now rising as the important issue. In this study suggests more efficient design for port gate automation.

• Transactions of Materials Processing
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• v.18 no.2
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• pp.160-165
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• 2009

A Study on Effects of the Runner and the Gate of double shot injection molded Parts using CAE Double shot injection molding can inject two different materials or two different colors in the same mold in a injection molding process. Double shot injection molded parts can be characterized that the base part maintains strength and specified part can inject soft-material. It can reduce the production cost by single automatic operations. In this paper, we designed double shot injection mold for automobile emote control To inject secondary part, this part is used as an insert after external appearance of product is injected. CAE analysis was progressed gate location and runner size as variables. The analysis result is reflected in mold design process. As a result, it could solve problems which are generated in the conventional mold. Additionally, cost can be downed by reducing runner weight. As well as it could omit painting process because the surface of finished product is improved through new mold.

• ETRI Journal
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• v.36 no.1
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.3
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.257-263
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• 2013

In this paper, Solar, Wind, fuel cell used in a Power conversion devices and industrial inverter motor to increase the efficiency of energy consumption, which is a core part of high-efficiency, high-voltage Trench Gate Field Stop IGBT was studied. For this purpose Planar type NPT IGBT and Planar type Field Stop IGBT have designed a basic structure designed to Trench Gate Field Stop IGBT based on the completed structure by analyzing the energy consumption of electrical characteristics, efficiency is a key part, high-efficiency and high-voltage inverter for industry regarding the optimization design for Trench Gate Field Stop IGBT.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2071-2077
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• 2010

Interface modules design between image sensor and external components are designed by FPGA (Field Programmable Gate Array) in this paper. Generally speaking, to satisfy synchronization for the poor quality data in image, SRAM is needed. To receive synchronization signal and image signal data with pixel dimension, the proposed interface logic technique is implemented. From the proposed technique, we can obtain more clear screen by implementing with pixel dimension. Operating frequency of image sensor and that of TFT-LCD are 50MHz and 6.5MHz, respectively. Most of control logic functions are embedded in FPGA. The designed logic gate counter has 33,216 and is designed by Quartus II.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.4
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• pp.313-320
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• 2003

This paper deals with the optimal design of a elevator inverter system based on the customized IPM. The proposed method reduces dv/dt and di/dt, which resulted in the minimized conducted EMI noise without an additional circuitry. It only optimizes the value of gate resistor in the IGBT embedded in the IPM. In order to optimize the customized IPM to a elevator system, we simulated and measured the spike voltage and the motor surge voltage including the temperature variation due to the switching losses at the IPM case and heat-sink. As a result, thanks to the optimized value of the gate resister in the IPM, the conducted EMI noise is reduced approx. 5∼10 [dB$\mu$V] in a particular frequency domain.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.751-754
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• 2003

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with pseudomorphic HEMTs. We have studied the calibration on the DC and RF characteristics of the MHEMT device using I $n_{0.53}$G $a_{0.47}$As/I $n_{0.52}$A1$_{0.48}$As modulation-doped heterostructure on the GaAs wafer. For the optimized device performance simulation, we calibrated the device performance of 0.1-${\mu}{\textrm}{m}$ $\Gamma$-gate MHEMT fabricated in our research center using the 2D ISE-DESSIS device simulator. With this calibrated parameter set, we have obtained very good reproducibility. The device simulation on the DC and RF characteristics exhibits good reproducibility for our 0.1-${\mu}{\textrm}{m}$ -gate MHEMT device compared with the measurements. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.ormance.

• Journal of Electrical Engineering and Technology
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• v.3 no.4
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• pp.566-570
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• 2008

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

• Journal of Navigation and Port Research
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• v.26 no.1
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• pp.127-136
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• 2002

This paper Presents a discussion on the design and realization for the Phase Sensitive Defector (PSD) circuitry of Flu$\chi$-gate Compass that gives direction information to the Directional Frequency Analysis and Recording (DIFAR) Sonobuoy in Air Anti-Submarine Warfare. PSD circuitry is realized with Twin-T RC networked active band-pass filter. Results of a performance test the PSD circuitry shows that the effectiveness of band-pass filtering of desired $2F_0$ second harmonic signal, which is Pro- portional to the direction of earth's magnetic field. This resulted in the extraction of direction information.