• Journal of Korean Society of Industrial and Systems Engineering
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• v.42 no.1
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• pp.1-7
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• 2019

In the modern industrial period, the introduction of mass production was most important progress in civilization. Die-casting process is one of main methods for mass production in the modern industry. The aluminum die-casting in the mold filling process is very complicated where flow momentum is the high velocity of the liquid metal. Actually, it is almost impossible in complex parts exactly to figure the mold filling performance out with the experimental knowledge. The aluminum die-castings are important processes in the automotive industry to produce the lightweight automobile bodies. Due to this condition, the simulation is going to be more critical role in the design procedure. Simulation can give the best solution of a casting system and also enhance the casting quality. The cost and time savings of the casting layout design are the most advantage of Computer Aided Engineering (CAE). Generally, the relations of casting conditions such as injection system, gate system, and cooling system should be considered when designing the casting layout. Due to the various relative matters of the above conditions, product defects such as defect extent and location are significantly difference. In this research by using the simulation software (AnyCasting), CAE simulation was conducted with three layout designs to find out the best alternative for the casting layout design of an automotive Oil Pan_BJ3E. In order to apply the simulation results into the production die-casting mold, they were analyzed and compared carefully. Internal porosities which are caused by air entrapments during the filling process were predicted and also the results of three models were compared with the modifications of the gate system and overflows. Internal porosities which are occurred during the solidification process are predicted with the solidification analysis. And also the results of the modified gate system are compared.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.732-741
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• 2018

In order to maximize the usable capacity of a BMS (battery management system) that uses several battery cells connected in series, a cell balancing technique that equips each cell with the same voltage is needed. In the active cell balancing circuit using a multi-winding transformer, a balancing circuit that transfers energy directly to the cell (cell-to-cell) is composed of a PMOS switch and a gate driving chip for driving the NMOS switch. The TLP2748 photocoupler and the TLP2745 photocoupler are required, resulting in increased cost and reduced integration. In this paper, instead of driving PMOS and NMOS switching devices by using photocoupler, we proposed 70V BCD process based PMOS gate driving circuit, NMOS gate driving circuit, PMOS gate driving circuit and NMOS gate driving circuit with improved switching time. ${\Delta}t$ of the PMOS gate drive switch with improved switching time was 8.9 ns and ${\Delta}t$ of the NMOS gate drive switch was 9.9 ns.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.6
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• pp.416-428
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• 1999

A user-interactive pixel design tool for high-quality TFT-LCDs is realized and used to explore the sensitivity of the various array and device parameters for optimizing pixel design. In this tool, the Thompson cable equation and gradual-channel approximation were used for the gate time delay and TFT current modeling respectively. With this tool, each capacitance element, and TFT and array dimensions can be optimized under given design specifications. The electrical characteristics such ascharging ratio, gate time delay, pixel voltage level-shift, and holding ratio can be analyzed. The sensitivity analysis of those design parameters were executed and presented.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.21 no.7
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• pp.84-90
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• 2022

The purpose of the cover housing component of a car door is to protect the terminals of the plug housing that connects the electric control unit on the door side to the car body. Therefore, for a smooth assembly with the plug housing and to prevent contaminants from penetrating into the gaps that occur after assembly, the warpage of the cover housing should be minimized. In this study, to minimize the warpage of the cover housing, optimization was performed for design factors related to the mold and processes based on the injection molding simulation. These design factors include gate location, gate diameter, injection time, resin temperature, mold temperature, and packing pressure. To optimize the design factors, Taguchi's approach to the design of experiments was adopted. The optimal combination of the design factors and levels that minimize warpage was predicted through L₁₈-orthogonal array experiments and main effects analysis. Moreover, the warpage under the optimal design was estimated by the additive model, and it was confirmed through the simulation experiment that the estimated result was quite consistent with the experimental result. Additionally, it was found that the warpage under the optimal design was significantly improved compared to both the warpage under the initial design and the best warpage among the orthogonal array experimental results, which numerically decreased by 36.9% and 23.4%, respectively.

• Journal of Dental Rehabilitation and Applied Science
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• v.31 no.3
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• pp.178-185
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• 2015

Purpose: The purpose of this study was to conduct a comparative assessment on the satisfaction level for the two interfaces of surgical guide system (SimPlant and R2GATE), the design and convenience of manufactured surgical guides and the importance of using the surgical guides thereof by means of survey. Materials and Methods: Hereupon, they simulated the implant surgical process by mounting the two manufactured systems of surgical guide on a dental mold, respectively. The study subjects were instructed to complete the questionnaire as to the satisfaction level upon completion of the simulated surgery. This study summarized the data of each question after collecting the completed questionnaires. Then, this study analyzed the summarized data by utilizing statistical program SPSS 20.0 (IBM). Results: R2GATE had a higher value of the satisfaction level on the design and convenience of manufactures surgical guides. R2GATE group ($7.33{\pm}1.26$) was found to have a higher value in terms of the overall satisfaction level compared to SimPlant group ($6.67{\pm}1.26$) (${\alpha}$ = 0.05). Conclusion: The user satisfaction level on the surgical guide manufactured for R2GATE system was to such an extent as it can be widely used in clinical environment. Moreover, the surgical guide manufactured as R2GATE system can guide both the length and direction of a drill simultaneously. As a result, it is highly recommended for those beginners who do not have a lot of experience in implant placement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.170-177
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• 2008

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1046-1049
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• 2002

In this paper, a sub-harmonic dual-gate FET mixer for IMT-2000 base-station was designed by using single-gate FET cascode structure and driven by the second order harmonic component of LO signal. The dual-gate FET mixer has the characteristic of high conversion gain and good isolation between ports. Sub-harmonic mixing is frequently used to extend RF bandwidth for fixed LO frequency or to make LO frequency lower. Furthermore, the LO-to-RF isolation characteristic of a sub-harmonic mixer is better than that of a fundamental mixer because the frequency separation between the RE and LO frequency is large. As RF power is -30dBm and LO power is 0dBm, the designed mixer shows the -47.17dBm LO-to-RF leakage power level, 10dB conversion gain, -0.5dBm OIP3, -10.5dBm IIP3 and -1dBm 1dB gain compression point.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.79-82
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• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials in existence coefficients over finite field GF(3$^{m}$ ). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of (m+1)$^2$identical cells, each cell consists of single mod(3) additional gate and single mod(3) multiplicative gate. Proposed multiplier need single mod(3) multiplicative gate delay time and m mod(3) additional gate delay time not clock. Also, the proposed architecture is simple, regular and has the property of modularity, therefore well-suited for VLSI implementation.