• Title/Summary/Keyword: Gate Current

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Electrical Characteristics of IGBT for Gate Bias under $\gamma$ Irradiation (게이트바이어스에서 감마방사선의 IGBT 전기적 특성)

  • Lho, Young-Hwan
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.2
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    • pp.1-6
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    • 2009
  • The experimental results of exposing IGBT (Insulated Gate Bipolar Transistor) samples to gamma radiation source show shifting of threshold voltages in the MOSFET and degradation of carrier mobility and current gains. At low total dose rate, the shift of threshold voltage is the major contribution of current increases, but for more than some total dose, the current is increased because of the current gain degradation occurred in the vertical PNP at the output of the IGBTs. In the paper, the collector current characteristics as a function of gate emitter voltage (VGE) curves are tested and analyzed with the model considering the radiation damage on the devices for gate bias and different dose. In addition, the model parameters between simulations and experiments are found and studied.

Novel properties of erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors

  • Jang, Moon-Gyu;Kim, Yark-Yeon;Shin, Jae-Heon;Lee, Seong-Jae;Park, Kyoung-Wan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.2
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    • pp.94-99
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    • 2004
  • silicided 50-nm-gate-length n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs) with 5 nm gate oxide thickness are manufactured. The saturation current is $120{\mu}A/{\mu}m$ and on/off-current ratio is higher than $10^5$ with low leakage current less than $10{\mu}A/{\mu}m$. Novel phenomena of this device are discussed. The increase of tunneling current with the increase of drain voltage is explained using drain induced Schottky barrier thickness thinning effect. The abnormal increase of drain current with the decrease of gate voltage is explained by hole carrier injection from drain into channel. The mechanism of threshold voltage increase in SB-MOSFETs is discussed. Based on the extracted model parameters, the performance of 10-nm-gate-length SB-MOSFETs is predicted. The results show that the subthreshold swing value can be lower than 60 mV/decade.

Electrical Characteristics of the Dual Gate Emitter Switched Thyristor (Dual Gate Emitter Switched Thyristor의 전기적 특성)

  • Kim, Nam-Soo;Lee, Eung-Rae;Cui, Zhi-Yuan;Kim, Yeong-Seuk;Kim, Kyoung-Won;Ju, Byeong-Kwon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.5
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    • pp.401-406
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    • 2005
  • Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

Double-Gate MOSFET Filled with Dielectric to Reduce Sub-threshold Leakage Current

  • Hur, Jae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.283-284
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    • 2012
  • In this work, a special technique called dielectric filling was carried out in order to reduce sub-threshold leakage current inside double-gated n-channel MOSFET. This calibration was done by using SILVACO Atlas(TCAD), and the result showed quite a good performance compared to the conventional double-gate MOSFET.

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A New Poly-Si TFT Employing Air-Cavities at the Edge of Gate Oxide (게이트 산화막 가장자리에 Air-cavity를 가지는 새로운 구조의 다결정 실리콘 박막 트랜지스터)

  • Lee, Min-Cheol;Jung, Sang-Hoon;Song, In-Hyuk;Han, Min-Koo
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.50 no.8
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    • pp.365-370
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    • 2001
  • We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

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A fabrication and characterization of asymmetric 0.1 ${\mu}{\textrm}{m}$ $\Gamma$-gate PHEMT device using electron beam lithography (전자선 묘화 장치를 이용한 비대칭적인 0.1 ${\mu}{\textrm}{m}$ $\Gamma$-게이트 PHEMT 공정 및 특성에 관한 연구)

  • 임병옥;김성찬;김혜성;신동훈;이진구
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.189-192
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    • 2001
  • We have studied fabrication processes that form asymmetric $\Gamma$-gate with a 0.1${\mu}{\textrm}{m}$ gate length in MMIC's(Monolithic Microwave Integrated Circuits). Asymmetric $\Gamma$-gate was fabricated using mixture of PMMA and MCB. Thus pseudomorphic high electron mobility transistor (PHEMT's) with 0.1${\mu}{\textrm}{m}$ gate length was fabricated via several steps such as mesa isolation, metalization, recess, passivation. PHEMT's has the -1.75 V of pinch-off voltage (Vp), 63 mA of drain saturation current(Idss and 363.6 mS/mm of maximum transconductance (Gm) in DC characteristics and current gain cut-off frequency of 106 GHz and maximum frequency of oscillation of 160 GHz in RF characteristics.

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Analysis of Anomalous Subthreshold Characteristics in Ligtly-Doped Asymmetric Double-Gate MOSFETs (Asymmetric Double-Gate MOSFET의 Subthreshold 특성 분석)

  • 이혜림;신형순
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.6
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    • pp.379-383
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    • 2003
  • The subthreshold characteristics of Double-Gate MOSFETs are analyzed for various Tsi. In the lightly-doped asymmetric device, it is found that the subthreshold current dramatically increases as the Tsi increases and this phenomenon is due to the linear distribution of potential in the channel region with low depletion-charge. Further, we derived an analytical equation which can explain this phenomenon and verified the accuracy of analytical equation by comparing with the result of device simulation.

A study on the dielectric characteristics improvement of gate oxide using tungsten policide (텅스텐 폴리사이드를 이용한 게이트 산화막의 절연특성 개선에 관한연구)

  • 엄금용;오환술
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.6
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    • pp.43-49
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    • 1997
  • Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

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Optimization and Characterization of Gate Electrode Dependent Flicker Noise in Silicon Nanowire Transistors

  • Anandan, P.;Mohankumar, N.
    • Journal of Electrical Engineering and Technology
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    • v.9 no.4
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    • pp.1343-1348
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    • 2014
  • The low frequency noise in Silicon Nanowire Field Effect Transistors is analyzed by characterizing the gate electrode dependence on various geometrical parameters. It shows that gate electrodes have a strong impact in the flicker noise of Silicon Nanowire Field effect transistors. Optimization of gate electrode was done by comparing different performance metrics such a DIBL, SS, $I_{on}/I_{off}$ and fringing capacitance using TCAD simulations. Molybdenum based gate electrode showed significant improvement in terms of high drive current, Low DIBL and high $I_{on}/I_{off}$. The noise power sepctral density is reduced by characterizing the device at higher frequencies. Silicon Nanowire with Si3N4 spacer decreases the drain current spectral density which interms reduces the fringing fields there by decreasing the flicker noise.

Signal Amplifying Gate Driver of Self-Excited Electronic Ballast for High Pressure Sodium (HPS) Lamp (고압 나트륨램프용 자려식 전자식 안정기의 신호 증폭형 게이트 구동회로)

  • Young, Yong-Sik;Cho, Gyu-Hyeong
    • Proceedings of the KIEE Conference
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    • 1996.07b
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    • pp.1304-1306
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    • 1996
  • A regenerative signal amplifying gate driver of self-excited electronic ballast is presented. It can be used for high pressure sodium (HPS) lamp without auxiliary external ignitor. Since the HPS lamp requires very high ignition voltage at start up, the resonant frequency of the circuit must be increased to obtain high voltage oscillations in spite of relatively small resonant current. The presented gate driver amplifies the current of gate drive transformer and raises the gate-source voltage Quickly to turn on the MOSFET switches. Hence, the resonant frequency can be increased more than 100kHz. The HPS lamp used in the simulation and experiment has the rating of 400W input power at 220V input ac voltage source. The experiments show that the resonant frequency is above 150kHz at start up.

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