• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.21-25
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to 4 V in the previous work. This is because the surface effect at the drain side decreases the channel current and the impact ionization in the channel at high drain voltage. In order to increase the breakdown voltage at the same asymmetric gate-recess structure, the InGaAs channel structure is replaced with the InGaAs/InP composite channel in the simulation. The simulation results with InGaAs/InP channel show that the breakdown voltage increases to 6V in the MHEMT as the current decreases. In this paper, the simulation results for the InGaAs/InP channel are shown and analyzed for the InGaAs/InP composite channel in the MHEMT.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.3
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• pp.217-221
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• 2011

GaAs-based and InP-based HEMTs(High Electron Mobility Transistors) have good microwave and millimeter-wave frequency performance with lower minimum noise figure. GaAs-based MHEMTs(Metamorphic HEMTs) have some advantages, especially for cost, compared with InP-based ones. In this paper, the RF small-signal circuits of MHEMTs are simulated and analyzed for the design of millimeter-wave application systems. The simulation analysis for RF small-signal frequency can help and give some insights about the MHEMTs for the design of millimeter-wave application and communication systems.

• Proceedings of the Korean Vacuum Society Conference
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• 1995.02a
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• pp.39-40
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• 1995

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.19-24
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• 2004

In this paper, we have demonstrated the fabrication of a 70 nm foot print of the T-gate by using a positive resist ZEP520/P(MMA-MAA)/PMMA trilayer by double exposure method without a thin dielectric supporting layer on the substrate. The device performance was characterized by DC and RF measurement. The fabricated 70 nm InGaAs/InAlAs MHEMTS with 70 ${\mu}{\textrm}{m}$ unit gate width and 2 fingers showed good DC and RF characteristics of Idss, max =228.6 mA/mm, gm =645 mS/mm, and fT =255 GHz, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.336-343
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• 2018

We herein present the design and fabrication of a Rx core chip operating in the X-band (10.5~13 GHz) using Win's commercial $0.25-{\mu}m$ GaAs pHEMT process technology. The X-band core chip comprises a low-noise amplifier, a four-bit phase shifter, and a serial-to-parallel data converter. The size is $1.75mm{\times}1.75mm$, which is the state-of-the-art size. The gain and noise figure are more than 10 dB but less than 2 dB, and both the input and output return losses are less than 10 dB. The RMS phase error is less than $5^{\circ}$, and the P1dB is 2 dBm at 12.5 GHz, the performance of which is equivalent to other GaAs core chips. The fabricated core chip was packaged in a QFN package type with a size of $3mm{\times}3mm$ for the convenience of assembly. We confirmed that the performance of the packaged core chip was almost the same as that of the chip itself.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.127-132
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• 2018

In this paper, a high conversion gain cascode mixer was designed in W-band and verified by the fabrication and measurements. In the high frequency band such as a W-band, the conversion loss of a mixer is increased because of the poor performance of transistors. This high conversion loss of the mixer requires additional circuits which can give an extra gain such as an RF buffer amplifier, and this can affects the linearity and stability of the overall systems. Therefore, it is necessary to maximize the conversion gain of the mixer. To maximize the conversion gain of the mixer, biases of the transistor were optimized, and output load impedance was optimized by the load-pull simulations. The designed mixer was fabricated in $0.1-{\mu}m$ GaAs pHEMT technology and verified by the measurements. The measurement results shows a maximum conversion gain of -4.7 dB at W-band and an input 1-dB compression point of 2.5 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.3
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• pp.171-183
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• 2018

Herein, we show the design and fabrication of a serial-to-parallel converter (SPC) using the $0.25-{\mu}m$ GaAs pHEMT process. The serial-to-parallel converter is composed of four bits to control the four phase shifters used in the core chip. The SPC stores the received serial data signal to a register in the SPC and converts the stored data into the parallel data. Each converted output data can control four phase shifters. The size of the fabricated SPC is $1,200{\times}480{\mu}m^2$ and it uses two DC power supplies of 5 V and -3 V. The consumption current of each DC power supply is 7.1 mA for 5 V, and 2.1 mA for -3 V.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.7
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• pp.56-61
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• 1997

I $n_{0.53}$G $a_{0.47}$As/I $n_{0.52}$A $l_{0.48}$As pseudomorphic high electron mobility transistor (P-HEMT) structures were grown on semi-insulating InP substrates by molecular beam epitzxy method. The hall effect measuremetn was used to measure the electrical properties and the photoluminescence (PL) measurement was used to measure the electrical properties and the photoluminescence(PL) measurement for optical propety. By the cross-sectional transmission electron microscopy (XTEM) investigation of the V and X shape defects including slip with angle of 60.deg. C and 120.deg. C to surface in the sampel, the defects formation mecahnism in the I $n_{0.52}$A $l_{0.48}$As epilayers on InP substrates could be explained with the different thermal expansion coefficients between I $n_{0.52}$A $l_{0.48}$As epilayers and InP substrate.d InP substrate.

• Journal of the Korean Vacuum Society
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• v.4 no.2
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• pp.177-182
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• 1995

저잡음 HEMT소자 제작을 위한 에피택셜 기판을 MBE방법을 이용하여 $In_{0.53}Ga_{0.47}As/In_{0.52}AI_{0.48}$As/InP 물질계로 성장하였다. 기판온도의 변화, 채널층과 격리층 사이의 성장 일시 멈춤 등의 성장 조건 변화에 따른 Hall 이동도의 변화를 연구하였다. 전자 공급층을 Si으로 델타도핑한 결과 같은 조건에서 성장기판의 온도를 $520^{\circ}C$에서$ 540^{\circ}C$로 증가시키면 실온의 전자이동도는 7,850$\textrm{cm}^2$/Vsec으로 증가하였으며, 격리층과 채널층 사이에서 약 50초간 성장중 채널층의 표면 adatom의 surface migration 시간을 충분히 제공하여 결정결함의 감소로 계면의 급격성이 향상된 결과로 사료된다. 본 실험을 통하여 얻은 최고 이동도 값은 격리층의 두께가 $100\AA$인 경유에 상온 측정결과 $11,400\textrm{cm}^2$/vsec 및 77K 측정결과 $50,300\textrm{cm}^2$/Vsec이었다.

• Journal of the Semiconductor & Display Technology
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• v.12 no.3
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• pp.23-27
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess structures has been simulated and analyzed for the breakdown of the devices with the InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2V to almost 4V and that the saturation current at gate voltage of 0V is reduced from 90mA to 60mA at drain voltage of 2V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier layer and the $Si_3N_4$ passivation layer deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer. In the paper, the fully-recessed asymmetric gate-recess structure at the drain side shows the on-breakdown voltage enhancement from 2V to 4V in the MHEMTs.