• Korean Journal of Materials Research
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• v.29 no.3
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• pp.155-159
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• 2019

Surface plasmon resonance is the resonant oscillation of conduction electrons at the interface between negative and positive permittivity material stimulated by incident light. In particular, when light transmits through the metallic microhole structures, it shows an increased intensity of light. Thus, it is used to increase the efficiency of devices such as LEDs, solar cells, and sensors. There are various methods to make micro-hole structures. In this experiment, micro holes are formed using a wet chemical etching method, which is inexpensive and can be mass processed. The shape of the holes depends on crystal facets, temperature, the concentration of the etchant solution, and etching time. We select a GaAs(100) single crystal wafer in this experiment and satisfactory results are obtained under the ratio of etchant solution with $H_2SO_4:H_2O_2:H_2O=1:5:5$. The morphology of micro holes according to the temperature and time is observed using field emission - scanning electron microscopy (FE-SEM). The etching mechanism at the corners and sidewalls is explained through the configuration of atoms.

• Journal of the Korean Chemical Society
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• v.48 no.6
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• pp.553-560
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• 2004

In this experiment, a three dimensional structure analysis was carried out to examine the surface defects of semiconductor made artificially on known scale. It was investigated the three dimensional imaging according to the sample depth and the thermal diffusivity as well as the carrier transport properties. The thermal diffusivity measurement of the intrinsic GaAs semiconductor was also analyzed by the difference of frequency-dependence photoacoustic signals from the sample surface of different conditions. Thermal properties such as thermal diffusion length or thermal diffusivity of the Si wafer with and without defects on the surface were obtained by interpreting the frequency dependence of the PA signals. As a result, the photoacoustic signal is found to have the dependency on the shape and depth of the defects so that their structure of the defects can be analyzed. This method demonstrates the possibility of the application to the detection of the defects, cracks, and shortage of circuits on surface or sub-surface of the semiconductors and ceramic materials as a nondestructive testing(NDT) and a nondestructive evaluation(NDE) technique.

• Korean Journal of Optics and Photonics
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• v.7 no.2
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• pp.150-156
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• 1996

RWG MQW-LD has been made with our vertical LPE system from the optimal design condition for the RWG MQW-LD to be activated as weakly index-guided LD. Through several experiments we have established the growth condition which can be used through to grow the MQW-DH wafer and to control the thickness of MQW layer to ~200$\AA$. 4 ${\mu}{\textrm}{m}$-thickness of the ridge pattern has been formed through the photolithographic process on the MQW-DH wafer grown by the former condition, and then we have fabricated the RWG MQW-LD using it. From the result of measuring the electro-optical characteristics we can make sure that it can be lasing as lasing as laterally single mode at even more than $2.7I_{th}$.

• Korean Journal of Materials Research
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• v.3 no.6
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• pp.645-651
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• 1993

The growth of semi-insulating(SI) high resistant undoped GaAs epilayer has been studied to solve the problems ocurring when GaAs IC is fabricated by the widely used ion implantation directly into the SI GaAs substrate. The EPD ditribution of the SI substrates has been examined, and the suitability of the buffer layers grown by MOCVD and MBE, respectively, has been tested for IC fabrication through leakage current measurement. IJngated FET has been fabricated on the SI epilayer and leakage current through the buffer layer has been measured. In the case of MOCVD grown 1$\mu\textrm{m}$-thick buffer layer, the leakage current is as small as about 270nA/mm, and this value does not affect the pinch-off of FET. In this case, the epilayer quality is affected by the substrate defects because the leakage current distribution is coincided with the EPD distribution of the SI substrate. The 2$\mu\textrm{m}$-thick buffer layer grown by MBE, however, has the better quality, and shows the lower leakage current(40nA/mrn) and higher uniformity.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.1
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• pp.329-332
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• 2012

LEDs are using widely in a field of illumination, LCD LED backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. To achieve high performance LEDs, one needs to enhance output power, reduce operation voltage, and improve device reliability. In this paper, we have proposed that the optimum design and specialized process could improve the performance of LED chip. It was showed an output power of 7cd and input supplied voltage of 3.2V by the insertion technique of current blocking layer. In this paper, GaN-based LED chip which is built on the sapphire epi-wafer by selective MOCVD were designed and developed. After that, their performances were measured. It showed the output power of 7cd more than conventional GaN-based chip. It will be used the lighting source of a medical equipment and LCD LED TV with GaN-based LED chip.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1135-1142
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• 2000

In this study, we fabricated a 1.55um polarization-insensitive semiconductor optical amplifier(SOA) with rectangular buried heterostructure using a InGaAsP/InP double heterostructure wafer. Measured characteristics of the fabricated SOA are that 3dR bandwidth is 35nm and 3dB saturation output power is 4dBm. Maximum gain under the 150mA CW driving condition is 19.4dB. We measured the ASE(amplified spontanouse emission) Power spectrum or n and TM mode in the fabricated SOA using ASE measurement system and knew that distributions of the TE and TM mode about the maxinum region are nearly coincident. this shows the fabricated SOA is a polarization-insensitive.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.383-389
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• 2001

We report on the design, fabrication, and characterization of 0.35${\mu}{\textrm}{m}$-gate AIGaAs/InGaAs PHEMTs for millimeter-wane applications. The epi-wafer structures were designed using ATLAS for optimum DC and AC characteristics, 0.351m-gate AIGaAs/rnGaAs PHEMTs having different gate widths and number of fingers were fabricated using electron beam lithography Dependence of RF characteristics of PHEMT on gate finger with and number of gate fingers have been investigated. PHEMT haying two 0.35$\times$60${\mu}{\textrm}{m}$$^2$ gate fingers showed the knee voltage, pinch-off voltage, drain saturation current density, and maximum transconductance of 1.2V, -1.5V, 275㎃/mm, and 260.17㎳/mm, respectively. The PHEMT showed fT(equation omitted)(current gain cut-off frequency) of 45㎓ and fmax(maximum oscillation frequency) of 100㎓. S$_{21}$ and MAG of the PHEMT were 3.6dB and 11.15dB, respectively, at 35㎓

• Korean Journal of Optics and Photonics
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• v.14 no.6
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• pp.669-673
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• 2003

We fabricated a buried-ridge waveguide laser diode (B-RWG LD) which has more advantages for obtaining lateral single mode operation on the same ridge width and for the planarization of the device surface, compared to the conventional RWG LD. In this LD, the difference of the lateral effective refractive index can be controlled by the thickness of the InGaAsP layer which is grown on the active and the p-InP layers. The InGaAsP multiple quantum well was grown on a n-InP substrate by the CBE. The buried ridge structure was formed by selective wet etchings, followed by liquid phase epitaxy methods. The fabricated LD with the ridge width of 7 ${\mu}{\textrm}{m}$ showed a linear increase of the optical power up to 20 ㎽ without any kinks and a saturated output power of more than 80 ㎽. By measuring the far field pattern, we demonstrate that LDs with the ridge widths of 5 ${\mu}{\textrm}{m}$ and 7 ${\mu}{\textrm}{m}$ were operated in a lateral single mode up to 2.7I$_{th}$ and 2.4I$_{th}$, respectively.ely.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.6
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• pp.486-491
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• 2000

The dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. But inferior goods are made under the influence of several parameters in dicing such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using neural network in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, five features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision, back-propagation neural network is adopted to classify the dicing process into normal and abnormal dicing, and normal and damaged blade. Experiments have been performed for GaAs semiconductor wafer in the case of normal/abnormal dicing and normal/damaged blade. Based upon observation of the experimental results, the proposed scheme shown has a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 6.5%.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.5
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• pp.70-75
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• 2000

After the patterning and probe process of wafer have been achieved, the dicing process is necessary to separate chips from a wafer. The dicing process cuts a wafer to lengthwise and crosswise direction to make many chips by using narrow circular rotating diamond blade. But inferior goods are made under the influence of complex dicing environment such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using feature extraction in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, two features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision. a threshold method is adopted to classify the dicing process into normal and abnormal dicing. Experiment have been performed for GaAs semiconductor wafer. Based upon observation of the experimental results, the proposed scheme shown a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 12.8%.