• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.889-893
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• 2015

In this work, the characteristics of GIDL current in nanowire GAA MOSFET with different channel width and hot carrier stress. When the gate length is fixed as a 250nm the GIDL current with different channel width of 10nm, 50nm, 80nm, and 130nm have been measured and analyzed. From the measurement, the GIDL is increased as the channel width decreaes. However, the derive current is increased as the channel width increases. From measurement results after hot carrier stress, the variation of GIDL current is increased with decreasing channel width. Finally, the reasons for the increase of GIDL current with decreasing channel width and r device. according to hot carrier stress GIDL's variation shows big change when width and the increase of GIDL current after hot carrier stress are confirmed through the device simulation.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.348-354
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• 2009

It has analyzed that the device degradation by NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOSFETs. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is govern by interface traps density at the silicon/oxide interface. from the relation between the variation of threshold voltage and subthreshold slope, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. Therefore, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

• Electrical & Electronic Materials
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• v.10 no.1
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1A
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• pp.80-86
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• 2010

This work has been measured and analyzed the device degradation of NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOS transistors of gate channel length 0.13 [${\mu}m$]. From the relation between the variation of threshold voltage and subthreshold slop by NBTI stress, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. As a results, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress parameters of nanoscale CMOS communication circuit design.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.77-87
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• 1993

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.285-285
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• 2011

최근 반도체 소자의 미세화에 따라, 단채널 효과에 의한 누설전류 및 소비전력의 증가 등이 문제되고 있다. 대표적인 휘발성 메모리인 dynammic random access memory (DRAM)의 경우, 소자의 집적화가 진행됨에 따라 저장되는 정보의 양을 유지하기 위해 캐패시터영역의 복잡한 공정을 요구하게 된다. 하나의 캐패시터와 하나의 트랜지스터로 이루어진 기존의 DRAM과 달리, single transistor (1T) DRAM은 silicon-on-insulator (SOI) 기술을 기반으로 하여, 하나의 트랜지스터로 DRAM 동작을 구현한다. 이러한 구조적인 이점 이외에도, 우수한 전기적 절연 특성과 기생 정전용량 및 소비 전력의 감소 등의 장점을 가지고 있다. 또한 strained-Si 층을 적용한 strained-Silicon-On-Insulator (sSOI) 기술을 이용하여, 전기적 특성 및 메모리 특성의 향상을 기대 할 수 있다. 본 연구에서는 sSOI 기판위에 1T-DRAM을 구현하였으며, impact ionization과 gate induced-drain-leakage (GIDL) 전류에 의한 메모리 구동 방법을 통해 sSOI 1T-DRAM의 메모리 특성을 평가하였다. 그 결과 strain 효과에 의한 전기적 특성의 향상을 확인하였으며, GIDL 전류를 이용한 메모리 구동 방법을 사용했을 경우 낮은 소비 전력과 개선된 메모리 윈도우를 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.352-352
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• 2012

MOSFET의 크기는 작아지고 다양한 소자열화 현상으로 신뢰성 문제가 나타나고 있다. 특히 CMOS 인버터에서 PMOS가 'HIGH'일 때 음의 게이트 전압이 인가되고 소자 구동으로 인해 온도가 높아지면 드레인 전류의 절대값은 줄어들고 문턱 전압 절대값과 GIDL전류가 증가하는 NBTI현상이 발생한다. 본 연구에서는 NBTI현상에 따른 열화 특성을 분석하였다. 측정은 드레인과 소스는 접지시킨 상태에서 온도 $100^{\circ}C$에서 게이트에 -3.4V과 -4V의 게이트 스트레스를 인가한 후 게이트 전압에 따른 드레인 전류를 스트레스 시간에 따라 측정하였다. 측정에 사용된 소자의 산화막 두께는 25A, 채널 길이는 $0.17{\mu}m$, 폭은 $3{\mu}m$이다. 게이트에 음의 전압이 가해지면 게이트 산화막에 양전하의 interface trap이 생기게 된다. 이로 인해 채널 형성을 방해하고 문턱 전압은 높아지고 드레인 전류의 절대값은 낮아지게 된다. 또한 게이트와 드레인 사이의 에너지 밴드는 게이트 전압으로 인해 휘어지게 되면서 터널링이 더 쉽게 일어나 GIDL전류가 증가한다. NBTI스트레스 시간이 증가함에 따라 게이트 산화막에 생긴 양전하로 인해 문턱 전압은 1,000초 스트레스 후 스트레스 전압이 각각 -3.4V, -4V일 때 스트레스 전에 비해 각각 -0.12V, -0.14V정도 높아지고 드레인 전류의 절대값은 5%와 24% 감소한다. GIDL전류 역시 스트레스 후 게이트 전압이 0.5V일 때, 스트레스 전에 비해 각각 $0.021{\mu}A$, $67{\mu}A$씩 증가하였다. 결과적으로, NBTI스트레스가 인가됨에 따라 게이트 전압 0.5V에서 0V사이의 드레인 전류가 증가함으로 GIDL전류가 증가하고 문턱전압이 높아져 드레인 전류가 -1.5V에서 드레인 전류의 절대값이 줄어드는 것을 확인할 수 있다.