• Proceedings of the Korean Information Science Society Conference
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• 2007.06d
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• pp.54-57
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• 2007

최근 멀티미디어 데이터 전송이 증가함에 따라 정보보호의 중요성이 대두되고 있으며, 기존의 데이터 전송시 암호화 뿐만 아니라, 안정적인 디지털 암호화 방법론과 컬러 영상 전송시 발생할 수 있는 원본 데이터의 중요성이 요구되고 있다. 따라서 본 논문에서는 정보 손실을 줄이기 위하여 주변 픽셀간의 변동폭이 심한 픽셀 단위의 암호화 방법이 아닌 컬러 영상 데이터 전송을 위해 영상 데이터의 각 프레임에 대한 암호화 기법을 제안한다. 또한 보다 안정된 암호화 방법으로 각 프레임에 대한 변형된 유한체 $GF(2^m)$상의 4bit 블록화를 통한 컬러 영상의 암호화 방법을 제안한다.

• Review of KIISC
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• v.4 no.1
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• pp.53-61
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• 1994

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.35-41
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• 2000

In this paper, the multiplicative algorithm of two polynomals over finite field GF(2$^{m}$ ) is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. This multiplier is consisted of three operation unit: multiplicative operation unit, the modular operation unit, the primitive irreducible operation unit. The multiplicative operation unit is composed of AND gate, X-OR gate and multiplexer. The modular operation unit is constructed by AND gate, X-OR gate. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and interconnection of the cells are regular, well-suited for VLSI realization.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.633-637
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• 2005

In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.331-336
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• 2004

This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1749-1754
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• 2013

Binary sequences of period $2^n-1$ are widely used in many areas of engineering and sciences. Some well-known applications include coding theory, code-division multiple-access (CDMA) communications, and stream cipher systems. In this paper we analyze different solutions to $x^5+bx^3+b^{2^m}x^2+1=0$ over $GF(2^n)$. The number of different solutions determines frequencies of cross-correlations of nonlinear binary sequences generated by $d=3{\cdot}2^m-2$, n=2m, m=4k($k{\geq}2$). Also we give an algorithm for determination of number of different solutions to the equation.

• Journal of the Society of Cosmetic Scientists of Korea
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• v.31 no.2 s.51
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• pp.161-167
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• 2005

We investigated the effect on inhibition of matrix metalloproteinase (MMP) in human dermal fibroblast (HDF) by production of exopolysaccharide (GF-glucan) from mycelial culture of Grifola frondosa HB0071. The photoprotective potential of GF-glucan was tested in HDF exposed to ultraviolet-A (UVA) light. It was revealed that GF-glucan had an inhibitory effect on MMP-1 expression in UVA-irradiated HDF without any significant cytotoxicity. The treatment of UVA-irradiated HDF with GF-glucan resulted in a dose-dependent degrease in the expression level of MMP-1 protein and mRNA (by maximum $54.4\%$ at an $0.5\%$ GF-glucan). These results suggest that GF-glucan obtained from mycelial culture of G. frondosa HB0071 may contribute to inhibitory action in photoaging by reducing the MMP-1 related matrix degradation system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.115-121
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• 2006

The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.