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VLSI Design of an Improved Structure of a $GF(2^m)$ Divider  

Moon San-Gook (목원대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.9, no.3, 2005 , pp. 633-637 More about this Journal
Abstract
In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.
Keywords
Elliptic Curve Cryptography; GF divider; VHDL; FPGA;
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