• Title/Summary/Keyword: GF($2^{m}$ )체

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Cell array multiplier in GF(p$^{m}$ ) using Current mode CMOS (전류모드 CMOS를 이용한 GF(P$^{m}$ )상의 셀 배열 승산기)

  • 최재석
    • Journal of the Institute of Convergence Signal Processing
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    • v.2 no.3
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    • pp.102-109
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    • 2001
  • In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.

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Efficient Algorithms for Finite Field Operations on Memory-Constrained Devices (메모리가 제한된 장치를 위한 효율적인 유한체 연산 알고리즘)

  • Han, Tae-Youn;Lee, Mun-Kyu
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.4
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    • pp.270-274
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    • 2009
  • In this paper, we propose an efficient computation method over GF($2^m$) for memory-constrained devices. While previous methods concentrated only on fast multiplication, we propose to reduce the amount of required memory by cleverly changing the order of suboperations. According to our experiments, the new method reduces the memory consumption by about 20% compared to the previous methods, and it achieves a comparable speed with them.

Design of High-Speed Parallel Multiplier with All Coefficients 1's of Primitive Polynomial over Finite Fields GF(2m) (유한체 GF(2m)상의 기약다항식의 모든 계수가 1을 갖는 고속 병렬 승산기의 설계)

  • Seong, Hyeon-Kyeong
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.2
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    • pp.9-17
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    • 2013
  • In this paper, we propose a new multiplication algorithm for two polynomials using primitive polynomial with all 1 of coefficient on finite fields GF($2^m$), and design the multiplier with high-speed parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $m^2$ same basic cells that have a 2-input XOR gate and a 2-input AND gate. Since the basic cell have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $D_A+D_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

New Division Circuit for GF(2m) Applications (유한체 GF(2m)의 응용을 위한 새로운 나눗셈 회로)

  • Kim Chang Hoon;Lee Nam Gon;Kwon Soonhak;Hong Chun Pyo
    • The KIPS Transactions:PartA
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    • v.12A no.3 s.93
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    • pp.235-242
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    • 2005
  • In this paper, we propose a new division circuit for $GF(2^m)$ applications. The proposed division circuit is based on a modified the binary GCD algorithm and produce division results at a rate of one per 2m-1 clock cycles. Analysis shows that the proposed circuit gives $47\%$ and $20\%$ improvements in terms of speed and hardware respectively. In addition, since the proposed circuit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Thus, the proposed divider. is well suited to low-area $GF(2^m)$ applications.

Efficient Serial Gaussian Normal Basis Multipliers over Binary Extension Fields

  • Kim, Yong-Tae
    • The Journal of the Korea institute of electronic communication sciences
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    • v.4 no.3
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    • pp.197-203
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    • 2009
  • Finite field arithmetic is very important in the area of cryptographic applications and coding theory, and it is efficient to use normal bases in hardware implementation. Using the fact that $GF(2^{mk})$ having a type-I optimal normal basis becomes the extension field of $GF(2^m)$, we, in this paper, propose a new serial multiplier which reduce the critical XOR path delay of the best known Reyhani-Masoleh and Hasan's serial multiplier by 25% and the number of XOR gates of Kwon et al.'s multiplier by 2 based on the Reyhani-Masoleh and Hasan's serial multiplier for type-I optimal normal basis.

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Design of Finite Field Multiplier based on KOA (KOA 기반의 유한체 승산기 설계)

  • Byun, Gi-Young;Na, Gi-Soo;Kim, Heung-Soo
    • Journal of IKEEE
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    • v.8 no.1 s.14
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    • pp.1-11
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    • 2004
  • This paper proposes new multiplicative techniques over finite field, by using KOA. At first, we regenerate the given polynomial into a binomial or a trinomial to apply our polynomial multiplicative techniques. After this, the product polynomial is archived by defined auxiliary polynomials. To perform multiplication over $GF(2^m)$ by product polynomial, a new mod $F({\alpha})$ method is induced. Using the proposed operation techniques, multiplicative circuits over $GF(2^m)$ are constructed. We compare our circuit with the previous one as proposed by Parr. Since Parr's work is premised on $GF((2^4)^n)$, it will not apply to general cases. On the other hand, the our work more expanded adaptive field in case m=3n.

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Efficient systolic VLSI architecture for division in $GF(2^m)$ ($GF(2^m)$ 상에서의 나눗셈연산을 위한 효율적인 시스톨릭 VLSI 구조)

  • Kim, Ju-Young;Park, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.3 s.357
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    • pp.35-42
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    • 2007
  • The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

A Fast Method for Computing Multiplicative Inverses in $GF(2^{m})$ Using Normal Basis ($GF(2^{m})$에서 정규기저를 이용한 고속 곱셈 역원 연산 방법)

  • 장용희;권용진
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 2002.11a
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    • pp.84-87
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    • 2002
  • 최근 정보보호의 중요성이 커짐에 따라 암호이론에 대한 관심이 증가되고 있다. 이 중 Galois 체 GF(2$^{m}$ )은 대부분의 암호시스템에서 사용되며, 특히 공개키 기반 암호시스템에서 주로 사용된다. 이들 암호시스템에서는 GF(2$^{m}$ )에서 정의된 연산, 즉 덧셈, 뺄셈, 곱셈 및 곱셈 역원 연산을 기반으로 구축되므로, 이들 연산을 고속으로 계산하는 것이 중요하다. 이들 연산 중에서 곱셈 역원이 가장 time-consuming하다. Fermat의 정리를 기반으로 하고, GF(2$^{m}$ )에서 정규기저를 사용해서 곱셈 역원을 고속으로 계산하기 위해서는 곱셈 횟수를 감소시키는 것이 가장 중요하며, 이와 관련된 방법들이 많이 제안되어 왔다. 이 중 Itoh와 Tsujii가 제안한 방법[2]은 곱셈 횟수를 O(log m)까지 감소시켰다. 본 논문에서는 Itoh와 Tsujii가 제안한 방법을 이용해서, m=2$^n$인 경우에 곱셈 역원을 고속으로 계산하는 방법을 제안한다. 본 논문의 방법은 필요한 곱셈 횟수가 Itoh와 Tsujii가 제안한 방법 보다 적으며, m-1의 분해가 기존의 방법보다 간단하다.

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The Optimal Normal Elements for Massey-Omura Multiplier (Massey-Omura 승산기를 위한 최적 정규원소)

  • 김창규
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.14 no.3
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    • pp.41-48
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    • 2004
  • Finite field multiplication and division are important arithmetic operation in error-correcting codes and cryptosystems. The elements of the finite field GF($2^m$) are represented by bases with a primitive polynomial of degree m over GF(2). We can be easily realized for multiplication or computing multiplicative inverse in GF($2^m$) based on a normal basis representation. The number of product terms of logic function determines a complexity of the Messay-Omura multiplier. A normal basis exists for every finite field. It is not easy to find the optimal normal element for a given primitive polynomial. In this paper, the generating method of normal basis is investigated. The normal bases whose product terms are less than other bases for multiplication in GF($2^m$) are found. For each primitive polynomial, a list of normal elements and number of product terms are presented.

A Study on Design of High-Speed Parallel Multiplier over GF(2m) using VCG (VCG를 사용한 GF(2m)상의 고속병렬 승산기 설계에 관한 연구)

  • Seong, Hyeon-Kyeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.3
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    • pp.628-636
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    • 2010
  • In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.