KOA 기반의 유한체 승산기 설계

Design of Finite Field Multiplier based on KOA

  • 변기영 (가톨릭대학교 정보통신전자공학부) ;
  • 나기수 (인하대학교 전자공학과) ;
  • 김흥수 (인하대학교 전자공학과)
  • Byun, Gi-Young (School of Information, Communication & Electronics Eng., Catholic Univ.) ;
  • Na, Gi-Soo (Dept. of Electronic Eng., InHa Univ.) ;
  • Kim, Heung-Soo (Dept. of Electronic Eng., InHa Univ.)
  • 발행 : 2004.07.01

초록

본 논문에서는 KOA를 적용하여 유한체 승산의 새로운 연산기법을 제시하였다. 먼저, 승산의 전개를 위해 주어진 다항식을 2분 또는 3분하여 각각 2항식과 3항식으로 재구성한 후 정의된 보조다항식을 사용하여 승산을 이루도록 하였다. 승산된 다항식에 모듈러 환원을 적용하기 위해 mod $F({\alpha})$ 연산식을 새롭게 전개하여 제시하였다. 제시된 연산기법들을 적용하여 $GF(2^m)$상의 승산회로를 구성하였고, Parr의 회로와 비교하였다. 비교논문의 경우 $GF((2^4)^n)$을 전제함으로써 그 적용이 매우 제한적이나, 본 논문에서는 $m=2^n$$m=3^n$인 경우를 보임으로써 그 적용이 Parr의 회로에 비해 보다 확장되었다.

This paper proposes new multiplicative techniques over finite field, by using KOA. At first, we regenerate the given polynomial into a binomial or a trinomial to apply our polynomial multiplicative techniques. After this, the product polynomial is archived by defined auxiliary polynomials. To perform multiplication over $GF(2^m)$ by product polynomial, a new mod $F({\alpha})$ method is induced. Using the proposed operation techniques, multiplicative circuits over $GF(2^m)$ are constructed. We compare our circuit with the previous one as proposed by Parr. Since Parr's work is premised on $GF((2^4)^n)$, it will not apply to general cases. On the other hand, the our work more expanded adaptive field in case m=3n.

키워드

참고문헌

  1. Error Control Coding Lin, S.
  2. BCH부호와 Reed-Solomon부호 이만영
  3. IEEE Trans. Computers v.37 no.6 A Comparison of VLSI Architecture of Field Multipliers Using Dual, Normal, or Standard Bases Hsu, I.S.;Troung, T.K.;Deutsch, L.J.;Reed, I.S.
  4. IEEE Trans. Computers v.C-20 no.12 A Cellular-Array Multiplier for GF(2m) Laws, B.A.;Rushford, C.K.
  5. IEEE Trans. Computers v.C-33 no.April Systolic Multipliers for Finite Field GF(2m) Yeh, C.S.;Reed, I.S.;Trung, T.K.
  6. IEEE Computer v.15 no.Jan. Why ssystolic architecture? Kung, H.T.
  7. Computational Method and Apparatus for Finite Fields Omura, J.;Massey, J.
  8. IEEE Trans. Computers v.C-34 no.Aug. VLSI Architecture for Computing Multiplications and Inverses in GF(2m) Wang, C.C.;Trung, T.K.;Shao, H.M.;Deutsch, L.J.;Omura, J.K.;Reed, I.S.
  9. IEEE Trans. on Information Theory v.IT-28 no.6 Bit-Serial Reed-Solomon Encoders Berlekamp, E.R.
  10. Sov. Phys.-Dokl. (Engl. transl.) v.7 no.7 Multiplication of Multidigit Numbers on Automata Karatsuba, A.;Ofman, Y.
  11. IEEE Trans. Computers v.45 no.7 A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields Parr, C.
  12. IEEE Trans. Computers v.47 no.2 Efficient Multiplier Architectures for Galois Fields GF(24n) Parr, C.;Fleischmann, P.;Roelse, P.
  13. VLSI Architectures for Multiplication in Galois Fields Mastrovito, E.D.
  14. IEEE Trans. Computers v.48 no.5 Mastrovito Multiplier for all trinomials Sunar, B.;Koc, C.K.