• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.3
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• pp.317-324
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• 2016

WiMedia provides the data rate of up to 1Gbps, but the transmission range is restricted to approximately 10 meters. When constructing a multi-hop WiMedia network to extend its coverage, conventional hop-based routing may not guarantee satisfactorily the required QoS. We propose two QoS routing techniques for the WiMedia-based wireless mesh network. The proopsed QoS routing reflects the characteristics of TDMA-based WiMedia MAC and develops QoS extensions separately for on-demand routing and table-driven routing. Through simulations, we identify that the QoS routing shows better performance than the hop-based routing. It also turns out that the QoS on-demand routing and the QoS table-driven routing show conflicting performance results depending on the transmission power.

• Journal of Advanced Navigation Technology
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• v.11 no.2
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• pp.177-186
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• 2007

In this paper, the optimal position offset of optical phase conjugator (OPC) and the optimal dispersion offsets of fiber sections, which are alternating with the method for the symmetry of optical power and chromatic dispersion with respect to OPC, are numerically investigated as afunction of the WDM channel numbers. The WDM channel numbers are assumed to be 8, 12, 16, 20 and 24. The bit-rate of each channel is assumed to be 40 Gbps for all cases. It is confirmed that the optimal position offset of OPC and optimal dispersion offset of fiber section are gradually increased as the WDM channel numbers are gradually increased. But, the optimal dispersion values of fiber sections per OPC position offset of 1 km are independent on WDM channel numbers, because the optimal position offset of OPC and optimal dispersion offset of fiber section are simultaneously increased as the WDM channel numbers are increased. It is also confirmed that the applying of these optimal parameter values is efficient to WDM system with many channels rather than WDM with small channels.

• Journal of the Korean Society for Railway
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• v.18 no.3
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• pp.223-231
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• 2015

This paper proposes a new wireless backhaul technology based on MHN(Mobile Hotspot Network) which uses a wide frequency band of millimeter wave to provide wideband Wi-Fi services for subway passengers. Performance analysis of MHN up and down links, based on data: up and down links structure analysis of physical layer and simulation study of the MHN wireless backhaul link model, show that the proposed MHN-based wireless backhaul network can transmit data at a 1.2Gbps data rate and provide Internet service 100 times faster than that of conventional WiBro-based wireless backhaul networks. These results indicate that the proposed MHN technology is appropriate for subway mobile networks.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.60-67
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• 2008

An all-optical 4-bit Gray code to binary coded decimal (BCD) converter by means of commercially available numerical analysis tool (VPI) was demonstrated, for the first time to our knowledge. Circuit design approach was modified appropriately in order to fit the electrical method on an all-optical logic circuit based on a cross gain modulation (XGM) process so that signal degradation due to the non-ideal optical logic gates can be minimized. Without regenerations, Q-factor of around 4 was obtained for the most severely degraded output bit (least significant bit-LSB) with 2.5 Gbps clean input signals having 20 dB extinction ratio. While modifying the two-level simplification method and Karnaugh map method to design a Gray code to BCD converter, a general design concept was also founded (one-level simplification) in this research, not only for the Gray code to BCD converter but also for any general applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6B
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• pp.456-468
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• 2008

In this paper, we design Input/Output modules as a preference work for implementation of hybrid two stage AWG based WDM-PON and verify operations of each function modules through the logic simulation. This WDM-PON system provides service to 128 ONUs through 32 wavelength and one wavelength is shared for upstream transmission with four ONU while each wavelength is allocated to each ONU for downstream transmission. The designed WDM-PON MAC chip is based on sub-MAC which consists of one control unit and reception unit and four transmission unit. To design the reception and transmission unit of sub-MAC, we define the functions of the sub-MAC, pins of the modules, control signal and timing of each signal. We intend to design MAC chip with 1Gbps transmission rate. Thus the designed MAC chip is worked on 125MHz clock rate. We define FSM and design Input/Output modules with VHDL. The logic simulation of the modules is executed by the ModelSIM simulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4B
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• pp.371-377
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• 2011

Users of the Information Age, IT usage patterns of the wired broadband information services and various forms of the same quality wireless multimedia services are required. Changes of these times the next-generation mobile communications (IMT-Advanced) has emerged as the necessity of developing its current voice and packet data communications on the move in the high-speed 100Mbps, 1Gbps in stationary and slow data transmission rates up to fixed-mobile convergence based on needed to provide ubiquitous service platform for the realization of IMT-Advanced is the time for preparation. In particular, 3-5GHz band, focused on mobile communications can be used to secure the necessary frequency band relocated and the existing crosstalk analysis methodology developed for the services rendered, and the frequency of such results to obtain new spectrum for IMT-Advanced for the country to secure the frequency characteristics and IMT-Advanced 3-5GHz band for the radio frequency of the characterization techniques necessary to develop a national wireless communication interference and frequency-based technology acquisition and management skills were identified.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.3
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• pp.495-504
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• 2012

This paper presents various speed optimization techniques for software implementation of the HIGHT block cipher on CPUs and GPUs. We considered 32-bit and 64-bit operating systems for CPU implementations. After we applied the bit-slicing and byte-slicing techniques to HIGHT, the encryption speed recorded 1.48Gbps over the intel core i7 920 CPU with a 64-bit operating system, which is up to 2.4 times faster than the previous implementation. We also implemented HIGHT on an NVIDIA GPU equipped with CUDA, and applied various optimization techniques, such as storing most frequently used data like subkeys and the F lookup table in the shared memory; and using coalesced access when reading data from the global memory. To our knowledge, this is the first result that implements and optimizes HIGHT on a GPU. We verified that the byte-slicing technique guarantees a speed-up of more than 20%, resulting a speed which is 31 times faster than that on a CPU.