• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1579-1588
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• 2014

The LAN method is the most widely used in domestic high-speed internet access and rapidly moving to 1 Gbps Ethernet from 100 Mbps one to provide high-speed services such as UHD TV. The 1000BASE-T PHY with 4 pairs UTP transmits a PAM-5 signal at the 125 MHz clock per each pair to achieve 1 Gbps rate. In order to correct errors over the channel, the transmitter uses a TCM which is combined the convolutional encoder and PAM-5, and the receiver uses the Viterbi decoder. In this paper, we implement a Viterbi decoder which can correct two pair errors and operate at the least 125 MHz clock speed. Finally, we will verify the error correction function and the operating speed of the implemented decoder with a logic analyzer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1C
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• pp.43-50
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• 2007

In the paper, we address QRM-MLD (Maximum Likelihood Detection with QR Decomposition and M-algorithm) signal detection method for spatially multiplexed MIMO (Multiple Input Multiple Output) systems. Recently, the QRM-MLD signal detection method which can achieve 1Gbps transmission speed for next generation mobile communication was implemented in a MIMO testbed for the mobile moving at a pedestrian speed. In the paper, we propose a novel signal detection method 'reduced complexity QRM-MLD' that achieves identical error performance as the QRM-MLD while reducing the computational complexity significantly. We rigorously compare the two detection methods in terms of computational complexity to show the complexity reduction of the proposed method. We also perform a set of computer simulations to demonstrate that two detection methods achieve identical error performance.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.6
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• pp.1145-1152
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• 2021

In order to optimize the performance of 1.4P large storage, the characteristics of each chunk mode were investigated, and the chunk 512K mode was selected in terms of I/O speed. NVME storage system was configured and used to measure data server performance of large storage. By measuring the change in throughput according to the number of threads of the 1.4P large storage, the characteristics of the large storage system were identified, and it was confirmed that the performance was up to 133Gbps with a block size of 32KB. As a result of data transmission/reception experiment using globus-url-copy of GridFTP, it was found that this large storage has a throughput of 33Gbps.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.351-355
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• 2010

The service which is required wide bandwidth is growing in these days, so building up High Speed communication system is being required. The Task Force team of IEEE 802.3ah set the EPON as a standard; next generation subscriber access network. For offering a high quality service, 10G EPON that is changed from 1Gbps uplink downlink bandwidth to 10Gbps is come up. Although Kramer had studied 10G EPON there was a QoS limitation, when load is low, End-to-End maximum delay is increased. This paper is suggesting time synch ronization method, resource reservation method, band width allocation method. We confirmed that 10EPON was able to offer quality service by the result of the OPNET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.587-594
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• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.170-178
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• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1354-1362
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• 2015

Heterogeneous network technology is expected to be a core technology for 5G mobile communications. 5G mobile network would be composed of many base stations even have mobility, then the operator should connect base stations through the wireless backhaul technology. This paper presents Ultra Wide Area Wireless Backhaul Network System with massive array antenna. We conducted link budget analysis for Ultra Wide Area Wireless Backhaul Network and performance analysis of massive array antenna system through the transmission simulator based on beamforming technology. In wide area ($10km^2$) wireless backhaul system composed of massive antenna, we achieved 5 bps/Hz average spectral efficiency with 1 W transmission power per beam.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.6
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• pp.77-87
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• 2001

This paper describes a design of cryptographic processor that implements the Rijndael cipher algorithm, the Advanced Encryption Standard algorithm. It can execute both encryption and decryption, and supports only 128-bit block and 128-bit keys. As the processor is implemented only one round, it must iterate 11 times to perform an encryption/decryption. We implemented the ByteSub and InvByteSub transformation using the algorithm for minimizing the increase of area which is caused by different encryption and decryption. It could reduce the memory size by half than implementing, with only ROM. We estimate that the cryptographic processor consists of about 15,000 gates, 32K-bit ROM and 1408-bit RAM, and has a throughput of 1.28 Gbps at 110 MHz clock based on Samsung 0.5um CMOS standard cell library. To our knowledge, this offers more reduced memory size compared to previously reported implementations with the same performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.786-792
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• 2016

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.28-33
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• 2006

An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.