• 한국전기전자재료학회논문지
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• 제27권2호
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• 한국전기전자재료학회논문지
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• 제32권5호
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• pp.366-370
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• 2019

In this paper, a single N+ emitter trench gate-type insulated gate bipolar transistor (IGBT) device was studied using T-CAD, in order to achieve a low on-state voltage drop (Vce-sat) and high breakdown voltage, which would reduce power loss and device reliability. Using the simulation, the threshold voltage, breakdown voltage, and on-state voltage drop were studied as a function of the temperature, the length of time in the diffusion process (drive-in) after implant, and the trench gate depth. During the drive-in process, a $20^{\circ}C$ change in temperature from 1,000 to $1,160^{\circ}C$ over a 150 minute time frame resulted in a 1 to 4 V change in the threshold voltage and a 24 to 2.6 V change in the on-state voltage drop. As a result, a 0.5 um change in the trench depth of 3.5 to 7.5 um resulted in the breakdown voltage decreasing from 802 to 692 V.

• 한국방사선학회논문지
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• 제13권3호
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• pp.453-458
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• 2019

본 연구에서는 Geant4 application for tomographic emission (GATE) 시뮬레이션 프로그램을 통해 설계 된 male adult mesh (MASH) 팬텀의 영상을 획득한 후 다양한 필터링 인자가 설정된 FNLM 노이즈 제거 알고리즘을 적용함으로써 그에 따른 영상 특성의 경향성을 알아보고자 한다. 이를 위해 GATE 시뮬레이션 프로그램을 통해 인체를 모사할 수 있는 MASH 팬텀을 설계하였다. 또한, 설계된 MASH 팬텀을 기반으로 MATLAB 프로그램을 통해 복부영상을 획득한 후 0.005의 $\sigma$ 값을 갖는 Gaussian noise를 추가하여 열화영상을 모델링하였다. 모델링 된 열화영상으로부터 제안하는 FNLM 노이즈 제거 알고리즘의 필터링 인자를 각각 0.005, 0.01, 0.05, 0.1, 0.5, 1.0 으로 설정하여 적용하였으며, 정량적 평가를 위해 FNLM 노이즈 제거 알고리즘이 적용된 영상들로부터 각각의 coefficient of variation (COV), signal to noise ratio (SNR) 그리고 contrast to noise ratio (CNR)을 측정하였다. 결과적으로, 0.05의 필터링 인자가 적용된 영상에서 가장 개선된 COV, SNR 그리고 CNR 값을 보였다. 특히, COV는 설정된 필터링 인자가 증가함에 따라 감소하였으며, 0.05 값 이후부터 거의 일정한 값을 나타내었다. 또한, SNR 및 CNR의 경우 필터링 인자가 증가함에 따라 증가하였으며, 0.05 값 이후부터 감소하는 경향을 보였다. 결론적으로, 열화 영상으로부터 FNLM 노이즈 제거 알고리즘 적용 시 적합한 필터링 인자를 설정해야 함이 증명되었다.

• Journal of Electrical Engineering and Technology
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• 제11권3호
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• pp.592-601
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• 2016

This paper presents the modeling of insulated-gate bipolar transistor (IGBT) in electromagnetic transients program (EMTP) simulation for the reliable calculation of switching and conduction losses. The conventional approach considering the physical property of switching devices requires many attribute parameters and large computation efforts. In contrast, the proposed method uses the curve fitting and interpolation techniques based on typical switching waveforms and a user-defined component with variable resistances to capture the dynamic characteristics of IGBTs. Therefore, the simulation time can be efficiently reduced without losing the accuracy while avoiding the extremely small time step, which is required in simulation by the conventional method. The EMTP based simulation includes turn-on and turn-off transients of IGBT, saturation state, forward voltage of free-wheeling diode, and reverse recovery characteristics, etc. The effectiveness of proposed modeling for the EMTP simulation is verified by the comparison with experimental results obtained from practical implementation in hardware.

• 전기전자학회논문지
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• 제24권1호
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• pp.194-199
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• 2020

본 논문에서는 비대칭 무접합 이중게이트 MOSFET에 대한 문턱전압이동을 상단과 하단 게이트 산화막 두께에 따라 분석하였다. 비대칭 구조에서는 상단과 하단 게이트 산화막 두께를 달리 제작할 수 있으므로 문턱전압이동을 일정하게 유지하면서 상단 게이트에서 발생할 수 있는 누설전류를 감소시키기 위하여 상단과 하단 산화막 두께를 조정할 수 있다. 이를 위하여 해석학적 문턱전압 모델을 제시하였으며 이 모델은 2차원 시뮬레이션 값과 잘 일치하였다. 결과적으로 일정한 문턱전압이동을 유지하면서 하단 게이트 산화막 두께를 감소시키면 상단 게이트 산화막 두께를 증가시킬 수 있어 상단 게이트에서 발생할 수 있는 누설전류를 감소시킬 수 있을 것이다. 특히 하단 게이트 산화막 두께가 증가하여도 문턱전압이동에는 큰 영향을 미치지 않는다는 것을 관찰하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

• ETRI Journal
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• 제34권4호
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• pp.633-636
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• 2012

A dynamic analysis of an amorphous silicon (a-Si) thin film transistor liquid crystal display (TFT-LCD) pixel is presented using new a-Si TFT and liquid crystal (LC) capacitance models for a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This dynamic analysis will be useful when predicting the performance of LCDs. The a-Si TFT model is developed to accurately estimate a-Si TFT characteristics of a bias-dependent gate to source and gate to drain capacitance. Moreover, the LC capacitance model is developed using a simplified diode circuit model. It is possible to accurately predict TFT-LCD characteristics such as flicker phenomena when implementing the proposed simulation model.

• 제어로봇시스템학회논문지
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• 제5권7호
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• pp.848-854
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• 1999

In this paper, we designed and implemented a precise pulse motor controller chip that generates the pulse needed to control step motor, DC servo and AC servo motors. This chip generates maximum pulse output rate of 5Mpps and has the quasi-S driving capability and speed and moving distance override capability during driving. We designed this chip with VHDL and executed a logic simulation and synthesis using Synopsys tool. The pre-layout simulation and post-layout simulation was executed by Compass tool. This chip was produced with 100 pins, PQFP package by 0.8${\mu}{\textrm}{m}$ gate array process and implemented by completely digital logic. We developed the test hardware board of performance and the CAMC(Computer Aided Motor Controller) Agent softwate to test the performance of the pulse motor controller chip produced. CAMC Agent enables user to set parameters needed to control motor with easy GUI(Graphic User Interface) environment and to display the output response of motor graphically.

• 전자공학회논문지A
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• 제31A권4호
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.247-253
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.