• 한국정보통신학회논문지
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• 제17권4호
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• pp.917-921
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• 2013

본 연구에서는 이중게이트 MOSFET의 전도중심에 따른 항복전압의 변화를 분석하였다. DGMOSFET에 대한 단채널효과 중 낮은 항복전압은 소자동작에 저해가 되고 있다. 항복전압분석을 위하여 포아송방정식의 분석학적 전위분포를 이용하였으며 이때 전하분포함수에 대하여 가우시안 함수를 사용함으로써 보다 실험값에 가깝게 해석하였다. 소자 파라미터인 채널길이, 채널두께, 게이트 산화막 두께 그리고 도핑농도 등에 대하여 전도중심의 변화에 대한 항복전압의 변화를 관찰하였다. 본 연구의 모델에 대한 타당성은 이미 기존에 발표된 논문에서 입증하였으며 본 연구에서는 이 모델을 이용하여 항복전압특성을 분석하였다. 분석결과 항복전압은 소자파라미터에 에 대한 전도중심의 변화에 크게 영향을 받는 것을 관찰할 수 있었다.

• 전자통신동향분석
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• 제35권2호
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• pp.79-88
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• 2020

Quantum computing is regarded as one of the revolutionary computing technologies, and has attracted considerable attention in various fields, such as finance, chemistry, and medicine. One of the promising candidates to realize fault tolerant quantum computing is quantum dot qubits, due to their expectation of high scalability. In this study, we briefly introduce the international tendencies for quantum dot quantum computing. First, the current status of quantum dot gate operations is summarized. In most systems, over 99% of single qubit gate operation is realized, and controlled-not and controlled-phase gates as 2-qubit entangling gates are demonstrated in quantum dots. Second, several approaches to expand the number of qubits are introduced, such as 1D and 2D arrays and long-range interaction. Finally, the current quantum dot systems are evaluated for conducting quantum computing in terms of their number of qubits and gate accuracies. Quantum dot quantum computing is expected to implement scalable quantum computing. In the noisy intermediate-scale quantum era, quantum computing will expand its applications, enabling upcoming questions such as a fault-tolerant quantum computing architecture and error correction scheme to be addressed.

• 정보처리학회논문지D
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• 제9D권1호
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• pp.145-152
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• 2002

현재 대부분의 가정이나 소규모 기업에서는 인터넷 서비스를 이용하기 위하여 ADSL(Asymmetric Digital Subscriber Line)나 케이블모뎀을 사용한다. 4바이트로 구성되는 현재의 인터넷 IP 주소체계(IPv4)에서는 할당 가능한 IP 주소가 부족하여, 동적으로 공인(Public) IP 주소를 할당하는 방식을 사용하고 있다. 이러한 동적인 IP 주소를 할당받는 시스템은 모든 인터넷 서비스를 이용하는 데에는 아무런 제약이 없지만, 자신이 각종 인터넷 서버 기능을 수행하는 데는 많은 문제점이 있다. 본 논문에서는 동적으로 변하는 IP 주소를 가진 시스템에서 인터넷 서버 서비스(Telnet, FTP, HTTP, Mail 등)가 가능하도록 하는 게이트웨이(Gate-D)를 설계하였으며, 실험적으로 Gate-D를 이용한 Telnet 서버의 구축을 통하여 유용성을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.213-216
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• 2003

Recently a new high power device GCT (Gate Commutated Turn-off) thyristor has been successfully introduced to high power converting application areas. GCT thyristor has a quite different turn-off mechanism to the GTO thyristor. All main current during turn-off operation is commutated to the gate. Therefore, IGCT thyristor has many superior characteristics compared with GTO thyristor; especially, snubberless tum-off capacibility and higher turn-on capacibility. The basic structure of the GeT thyristor is same as that of the GTO thyristor. This makes the blocking voltage higher and controllable on-state current higher. The turn-off characteristic of the GCT thyristor is influenced by the minority carrier lifetime and the performance of the gate drive unit. In this paper, we present turn-off characteristics of the 2.5kV PT(Punch-Through) type GCT as a function of the minority carrier lifetime and variation of the doping profile shape of p-base region.

• 한국위성정보통신학회논문지
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• 제8권2호
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• pp.36-43
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• 2013

본 논문에서는 고전압에서 동작하는 DDIC(display driver IC) 칩의 정전기 보호소자로 사용되는 GG_EDNMOS 소자의 고전류 특성 및 더블 스냅백 메커니즘이 분석되었다. 이온주입 조건을 달리하는 매트릭스 조합에 의한 수차례의 2차원 시뮬레이션 및 TLP 특성 데이타를 비교한 결과, BJT 트리거링 후에 더블 스냅백 현상이 나타났으나 웰(well) 및 드리프트(drift) 이온주입 조건을 적절히 조절함으로써 안정적인 ESD 보호성능을 얻을 수 있었다. 즉, 최적의 백그라운드 캐리어 밀도를 얻는 것이 고전압 동작용 정전기보호소자의 고전류 특성에 매우 중요한 영향을 주는 임계인자(critical factor)임을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.25-28
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• 1999

Metal ferroelectric semiconductor Field Effect- Transistors(MFSFET) with various gate electrodes, that are aluminum, platinum and poly -Si, using LiNbO$_3$/Si(100) structures were fabricated and the properties of the FETs have been discussed. The drain current of the state of FET with Pt electrode was more than 3 orders of magnitude larger than the state current at the same gate voltage of 1.5 V, 7.rich means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about 10$^3$s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• Current Applied Physics
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• 제18권12호
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• pp.1546-1552
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• 2018

The polymer nanocomposite as a gate dielectric film was prepared via sol-gel method. The formation of crosslinked structure among nanofillers and polymer matrix was proved by Fourier transform infrared spectroscopy (FT-IR). Differential thermal analysis (DTA) results showed significant increase in the thermal stability of the nanocomposite with respect to that of pure polymer. The nanocomposite films deposited on the p- and n-type Si substrates formed very smooth surface with rms roughness of 0.045 and 0.058 nm respectively. Deconvoluted $Si_{2s}$ spectra revealed the domination of the Si-OH hydrogen bonds and Si-O-Si covalence bonds in the structure of the nanocomposite film deposited on the p- and n-type Si semiconductor layers respectively. The fabricated n-channel field-effect-transistor (FET) showed the low threshold voltage and leakage currents because of the stronger connection between the nanocomposite and n-type Si substrate. Whereas, dominated hydroxyl groups in the nanocomposite dielectric film deposited on the p-type Si substrate increased trap states in the interface, led to the drop of FET operation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.236-241
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• 2001

This paper presents a novel prototype of active voltage-clamping capacitor-assisted edge resonant soft switching PWM inverter operating at a constant frequency variable power (VPCF) regulation scheme, which is suitable for consumer high-power induction-heating cooking appliances. New generation IGBT with a trench gate is particularly improved in order to reduce conduction loss due to its lowered saturation voltage characteristics. The soft switching load resonant and quasi-resonant inverter designed distinctively using the latest IGBTs is evaluated from an experimental point of view.

• Journal of Power Electronics
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• 제7권4호
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.