• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.6 no.3
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• pp.115-125
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• 2001

To examine the movement of the freshwater discharged artificially into the estuary during ebbing period in the Keum River dike we observed surface salinity variations in three stations along the estuary channel in May 1998 and July 1997 and surface temperature and salinity along the ferry-route between Kunsan and Changhang during eighteen days in July 1999. Based upon the typical features of observed salinity variation, we analyzed the excursion and decay processes of the discharged water. When freshwater is discharged, the low-salinity water forms strong salinity front over the entire estuary width, which basically moves forth and back by tidal modulation along the channel, producing the sudden change of surface salinity with the front passage. Salinity distribution along the channel, which is deduced from time variation of mean salinity over the estuary width, after one tidal period from gate operation suggests that diluted low-salinity water is trapped to the front and surface salinity increases gradually toward the upstream region. This frontal distribution of salinity is interpreted to be produced by the sudden gate operation supplying and stopping of freshwater within about two hours. Daily repeat of freshwater discharge produces separation (double front) or merge between decaying and new-generated fronts depending on dike-gate opening time, and the front decays with salinity increasing if the freshwater supply is stopped more than two days. In addition, the observed fluctuations and deviations in surface salinity variation is explained in terms of the differences of fronts intensity, their transition time and temporal salinity front running along the channel, which can be generated due to artificial gate-operation for the discharging time and water volume in the estuary dike.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.9-15
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• 2005

In this research the discharge characteristics of logic gate of the discharge logic gate plasma display panel with the NOT-AND logic function newly designed was analyzed. As for this discharge logic gate a logical output is induced by controlling the voltage between the electrodes using the discharge path. From the experimental result the discharge characteristics of logic gate is influenced by the interrelation of the voltages appling two vertical electrodes. To in the application possibility to large screen PDP, the discharge characteristics by the line resistance of the electrode was evaluated In result it has been inferred that the influence which the drop of voltage by the line resistance of two vertical electrodes exerts on the discharge of the logic gate is minute. Through the experiment, the optimized values of the pulse voltages and the current limitation resistances of each electrode which composed the discharge logic gate were obtained and maximum operation margin of 49[V] was obtained.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.48.1-48.1
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• 2009

Performance of organic field-effect transistors (OFETs) with various temperature-cured polyacrylate(PA) copolymer as a gate insulator was studied. The PA thin film, which was cured at an optimized temperature, showed high dielectric strength (>7 MV/cm), low leakage current density ($5{\times}10^{-9}\;A/cm^2$ at 1 MV/cm) and enabled negligible hysteresis in MIS capacitor and OFET. A field-effect mobility of ${\sim}0.6\;cm^2/V\;s$, on/off current ratio (Ion/Ioff) of ${\sim}10^5$ and inverse subthreshold slope (SS) as low as 1.22 V/decwere achieved. The high dielectric strength made it possible to scale down the thickness of dielectric, and low-voltage operation of -5 V was successfully realized. The chemical changes were monitored by FT-IR. The morphology and microstructure of the pentacene layer grown on PA dielectrics were also investigated and correlated with OFET device performance.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1117-1126
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• 2017

The main contribution of this paper is the use of sensorless active diodes to generate the gate signals for a three-phase boost-rectifier with a self-powered control scheme. The sensorless operation is achieved making use of the gate control signals generated by the active diode schemes on each of the switching devices using a pulse width half-controlled boost rectifier modulation technique (PWM-HCBR). The proposed scheme synchronizes the gate control signals with a three phase voltage supply. Autonomous operation is obtained making use of the output DC bus to feed the control circuitry, the active diodes and the driver circuitry. The three-phase boost-rectifier is supplied by a three-phase permanent magnet electric generator powered by a solar concentrator dish with variable voltage and variable frequency conditions. Experimental results report an efficiency of up to 94.6% for 25 W and an input of 3.6 V peak per phase with 450.

• Journal of Sensor Science and Technology
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• v.27 no.6
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• Journal of Navigation and Port Research
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• v.40 no.6
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• pp.421-430
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• 2016

In this study, a gate simulation model was developed to reduce the truck waiting time for trucking companies servicing container terminals. To verify the developed model, 4 weeks of truck gate-in/gate-out data was collected in December 2014 at the Port of Busan New Port. Also, the existing gate system was compared to the proposed gate system using the developed simulation model. The result showed that based on East gate-in, a maximum number of 50 waiting trucks with a maximum waiting time of 120 minutes. With the proposed system the maximum number of waiting trucks was 10 with a maximum waiting time of 5.3 minutes. Based on West gate-in, the maximum number of waiting trucks was 17 and the maximum waiting time was 34 minutes in the existing gate system. With the proposed system the maximum number of waiting trucks was 10 with a maximum waiting time of 5.3 minutes. Based on West gate-out, the maximum number of waiting trucks was 11 with a maximum waiting time of 5.5 minutes. With the proposed system the maximum number of waiting trucks was 9 with a maximum waiting time of 4.4 minutes. This developed model shows how many waiting trucks there are, depending on the gate-in/gate-out time of each truck. This system can be used to find optimal gate system operating standards by assuming and adjusting the gate-in/gate-out time of each truck in different situations.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.64-70
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• 1995

A new DC drain-current model of GaAs MESFET with improved accuracy is proposed in this paper. The proposed model includes the decrease of current slope according to gate voltages. It is possible to represent a transconductance compression using the proposed model. It shows improved transconductance and output resistance in accuracy from the forward biased gate region to near the cutoff region. The wquaer error of saturation current is decreased by 46% compared with Statz model. The proposed model can be useful for the simulation of large-signal operation and harmonic distortion.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.38-45
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• 2020

With the recent emergence of foldable electronic devices, interest in flexible organic memory is significantly growing. There are three types of flexible organic memory that have been researched so far: floating-gate (FG) memory, ferroelectric field-effect-transistor (FeFET) memory, and resistive memory. Herein, performance parameters and operation mechanisms of each type of memory device are introduced, along with a brief summarization of recent research progress in flexible organic memory.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.52-56
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• 2014

In this paper, a high-efficiency power amplifier is implemented using a gate and drain bias control circuit for WPT (Wireless Power Transmission). This control circuit has been employed to improve the PAE (Power Added Efficiency). The gate and drain bias control circuits consists of a directional coupler, power detector, and operation amplifier. A high gain two-stage amplifier using a drive amplifier is used for the low input stage of the power amplifier. The proposed power amplifier that uses a gate and drain bias control circuit can have high efficiency at a low and high power level. The PAE has been improved up to 80.5%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.1
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• pp.16-20
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• 2020

In this study, a patterning method using self-aligned nanostructures was introduced to fabricate GaN-based fin-gate HEMTs with normally-off operation, as opposed to high-cost, low-productivity e-beam lithography. The honeycomb-shaped fin-gate channel width is approximately 40~50 nm, which is manufactured with a fine width using a proposed method to obtain sufficient fringing field effect. As a result, the threshold voltage of the fabricated device is 0.6 V, and the maximum normalized drain current and transconductance of Gm are 136.4 mA/mm and 99.4 mS/mm, respectively. The fabricated devices exhibit a smaller sub-threshold swing and higher Gm peak compared to conventional planar devices, due to the fin structure of the honeycomb channel.