• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.107-116
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• 1994

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.385-388
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• 2009

We have investigated the effect of the device structure on the performance of polycrystalline ZnO TFT and amorphous AZTO TFT with top gate and bottom gate structure. While the mobility of both TFTs showed relatively similar value in a top and bottom gate structure, bias stability was quite different depending on the device structure. Top gate TFT showed much less Vth shift under positive bias stress compared to that of bottom gate TFT. We attributed this different behavior to the defects formation on the gate insulator induced by energetic bombardment during the active layer deposition in a bottom gate TFT. We suggest the top gate oxide TFT would show more stable behavior under the Vgs bias.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.202-209
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• 2000

This paper introduces the main function and protection method of IGBT gate driver that designed by KOROS. Recently, the applications of insulated gate bipolar transistors(IGBTs) have expanded widely, particularly in the area of railway converters. This driver is suitable for railway traction applications, so they are designed for circumstance of railway vehicle such as vibration. The input control power for this driver is supplied from battery charger of railway. it is no necessary an isolated power supply board or auxiliary power supply, with substantial savings in cost and space in railway applications. This gate driver can be used wide range of input voltage. So, performance of the driver has no relation with the battery voltage(70V∼110V). The protection methods of IGBT gate driver have many kind of ways, but this gate driver it designed to apply to converter for railway system, so this gate driver includes protection for arm short current and low control power voltage, etc. And the process of protection method and protection reference value are optimized by means of sufficient test with our own facilities.

• Journal of IKEEE
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• v.19 no.4
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• pp.514-519
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• 2015

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.45-49
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• 2007

The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

• Journal of Navigation and Port Research
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• v.31 no.9
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• pp.771-778
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• 2007

A container terminal gate is not only an entrance of containers, but also the first input point of containers' information. Therefore, to achieve the accuracy of container information, there are various containers' numbers recognition methods used. Gate productivity can significantly vary depending upon those recognition methods. Recently, RFID which is one of the u-IT businesses run by the Korean government is under consideration for application to the gate as an automatic system. If RFID is used, it is expected to have both the qualitative benefits through avoiding defects of other systems and the quantitative benefits by improving productivity. Hence, this study aims to provide some insight on the benefits of RFID, and to compare productivity of the existing gate system with the RFID gate system based on computer simulation.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.1974-1976
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• 2005

The feasibility of a midgap metal gate is investigated for 32nm MOSFET low power applications. The midgap metal gate MOSFET is found to deliver a driving current as high as a bandedge gate one for the low power applications if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in ITRS roadmap. In addition, a process simulation is run using halo implants and thermal processes to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. From the thermal budget point of view, the bandedge metal gate MOSFET is more vulnerable to the following thermal process than the midgap metal gate MOSFET since it requires a steeper retrograde doping profile. Based on the results, a guideline for the gate workfunction and the channel profile in the 32 nm MOSFET is proposed.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.87-93
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• 2020

This study proposes a gate driver that operates semiconductor switches in the bipolar pulsed power modulator. The proposed gate driver was designed to receive isolated power and synchronized signals through the gate transformer. The gate circuit has a separate delay in the on-and-off operation to prevent a short circuit between the top and bottom switches of each leg. On the basis of the proposed gate circuit, a bipolar pulsed power modulator prototype with a 2.5 kV/100 A rating was developed. Finally, the bipolar pulsed power modulator was tested under resistive load and plasma reactor load conditions. It is verified that the proposed gate driver can be applied to a bipolar pulsed power modulator.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.173-174
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• 2006

In this paper we proposed transient model for NPT(Non Punch-Through) IGBT(Insulated Gate Bipolar Transistor) with gate resistances. As gate resistance increases, turn-off time increases. But If gate resistance is small, overshoot voltage increase. To analyze the effect of gate resistance, the transient model is made and the experiments are conducted. We used gate resistances of values; 8[$\Omega$], 140[$\Omega$], 810[$\Omega$] for simulations and experiments. We compared theoretical and experimental results and obtained good agreements.

• Journal of Navigation and Port Research
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• v.40 no.6
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• pp.421-430
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• 2016

In this study, a gate simulation model was developed to reduce the truck waiting time for trucking companies servicing container terminals. To verify the developed model, 4 weeks of truck gate-in/gate-out data was collected in December 2014 at the Port of Busan New Port. Also, the existing gate system was compared to the proposed gate system using the developed simulation model. The result showed that based on East gate-in, a maximum number of 50 waiting trucks with a maximum waiting time of 120 minutes. With the proposed system the maximum number of waiting trucks was 10 with a maximum waiting time of 5.3 minutes. Based on West gate-in, the maximum number of waiting trucks was 17 and the maximum waiting time was 34 minutes in the existing gate system. With the proposed system the maximum number of waiting trucks was 10 with a maximum waiting time of 5.3 minutes. Based on West gate-out, the maximum number of waiting trucks was 11 with a maximum waiting time of 5.5 minutes. With the proposed system the maximum number of waiting trucks was 9 with a maximum waiting time of 4.4 minutes. This developed model shows how many waiting trucks there are, depending on the gate-in/gate-out time of each truck. This system can be used to find optimal gate system operating standards by assuming and adjusting the gate-in/gate-out time of each truck in different situations.