• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.41 no.3
• /
• pp.72-82
• /
• 2018

In this paper, we identify risk factors that are likely to occur during the lifecycle of a new product development (NPD) project from the literatures, and identify the three objectives or three constraints that will ultimately be achieved for project success in the ICT industry : performance (scope/quality), schedule (time), and cost. Firstly, we interviewed the project experts to classify the risk factors according that the final project objectives are changeable based on scope/quality, time and cost budget constraints. Secondly, the survey for pairwise comparisons between the risk factors was asked to the project managers and members who had ever actually participated in the NPD projects of ICT industry to determine the priority ranks on relative importance using AHP (Analytic Hierarchy Process). The risk factors negatively affecting the goals of projects were analyzed by using the AHP respectively in four project stages during the life cycle of the project. The comparison of risk factors within each stage is a different approach unlike the literatures which have covered project's overall risk assessment. There is an advantage that risk management can be effectively performed with priorities according to each stage from the start to the end of the project. In other words, it is necessary to identify what risk factors will occur in each stage, and to have ideas at each stage with the priorities so that they can be mitigated and eliminated before actual occurrence. As a result, risks on scope & quality changes were found to be the most important considerations for initiative stage of NPD projects in the ICT industry, whereas in the final stage, risks on schedule (time) changes were the most important priorities. Among the ICT industry product categories, 'communication and broadcasting devices' and 'IT and communication based devices' generally have a high priority in terms of risks on scope & quality changes when initiating the project. At the closing stage of the project, however, considering that schedule (time) changeable risk is getting higher, these products tend to target at B2B market rather than B2C because the new products must be delivered and launched in time as customer firm required.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.42 no.2 s.302
• /
• pp.49-58
• /
• 2005

A new soft switching three-phase PWM rectifier with simple circuit configuration and high efficiency has been developed. The proposed circuit is a kind of the auxiliary resonant commutated Pole(ARCP)converter The conventional ARCP converter requires three-auxiliary reactors and six-auxiliary switches for the soft switching auxiliary circuit and for these switching elements, a gate drive circuit and a control circuit are required, resulting in high part as a disadvantage. In the main circuit proposed in this paper, the auxiliary soft switching circuit is composed of two-auxiliary reactors, two-auxiliary switches and several diodes. In addition, common use of the PWM control circuit for two-switches will make the control circuit of the auxiliary switches simple. By means of function of the soft switching auxiliary circuit, the main switching element performs zero voltage switching operation and the auxiliary switches perform the zero current switching. In this paper, the circuit configuration and the operational analysis of the proposed circuit are described at first and then, experimental results will be reported. By using a prototype with 5[kW] capacity, the conversion efficiency of maximum $98.8[\%]$ and the power factor of $99[\%]$ or higher were obtained.

• Journal of architectural history
• /
• v.16 no.6
• /
• pp.121-140
• /
• 2007

Seowon(書院) is a representing institution in Choseon Dynasty not only educationally but also politically and economically. Due to the artificial crackdown by Daewon-gun in 1871 and destruction by wars, it is difficult to restore and interpret the Seowon accurately at present. It is well known that the 'Basic Form' of the Seowon consists of an inner court, enclosed by the rear gangdang (lecture hall), dongseo-jae (east and west dormitory), and the front munlu (gate pavilion or upper story bower for relaxation), represented by so called 'front-dormitory rear-lecture-hall type', that is, 'jeonjae hudang(前齋後堂) type'. However, it is overlooked that this Basic Form is a product of Youngnam School located only in Youngnam area. A different form, of 'front-lecture-hall rear-dormitory type', or 'jeonndang hujae(前堂後齋) type' is located only in Gyeonggi, Hoseo and Honam area. It has been wrongly analyzed that the type is a result of the later period, emphasizing the memorial service rather than the lecture itself, and worshipping loyalists than Confucian scholars. Analysis encompassing each Seowon architecture has been mistakenly made by historians as "deterioration" of the original educational purpose of the Seowon from the early period to the later period. This paper raises the fact that the form of jeondang hujae type has been established since the early period of Seowon in the 16th Century. It has a unique order of space itself. Here, the lecture hall faces toward sadang (shrine). The inner court, enclosed by east and west jae and the lecture hall, becomes the outer yard of the shrine, and as a result two main spaces of the shrine and lecture area is merged into one. While the munlu of the basic type encloses the inner court of the main area, the munlu of jeondang hujae type is located at the vicinity area. This paper reinterprets the jeondang hujae type not as a form coming out of degenerated period but as a type that belongs to a different Confucian school, the area of Kiho, and concludes that the Seowon is a product of political struggles between the two schools and of the local economical situation. Each school has maintained his own type of form, therefore the remaining Kiho Seowon architecture can be reevaluated.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.7
• /
• pp.455-463
• /
• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.6 s.348
• /
• pp.47-52
• /
• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.38 no.3
• /
• pp.40-46
• /
• 2001

In this paper, a novel low power full adder circuit comprising only 10 transistors is proposed. The circuit is based on the six -transistor CMOS XOR circuit, which generates both XOR and XNOR signals and pass transistors. This adder circuit provides a good low power characteristics due to the smaller number of transistors and the elimination of short circuit current paths. Layouts have been carried out using a 0.65 ${\mu}m$ ASIC design rule for evaluation purposes. The physical design has been evaluated using HSPICE at 25MHz to 50MHz. The proposed circuit has been used to build 2bit and 8bit ripple carry adders, which are used for evaluation of power consumption, time delay and rise and fall time. The proposed circuit shows substantially improved power consumption characteristics, about 70% lower than transmission gate full adder (TFA), and 60% lower than a design using 14 transistors (TR14). Delay and signal rise and fall time are also far shorter than other conventional designs such as TFA and TR14.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.5
• /
• pp.102-111
• /
• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.5
• /
• pp.796-805
• /
• 2000

A 30GHz band low noise amplifier module, which has linear gain of 30dB and noise figure of 2.6dB, for 30GHz satellite communication transponder was developed by use of MMIC and thin film MIC technologies. Two kinds of MMIC circuits were used for the low noise amplifier module, the first one is ultra low noise MMIC circuit and the other is wideband and high gain MMIC circuit. The pHEMT technology with 0.15$mu extrm{m}$ of gate length was applied for MMIC fabrication. Thin film microstrip lines on alumina substrate were used to interconnect two MMIC chips, and the thick film bias circuit board were developed to provide the stabilized DC bias. The input interface of the low noise amplifier module was designed with waveguide type to receive the signal from antenna directly, and the output port was adopted with K-type coaxial connector for interface with the frequency converter module behind the low noise amplifier module. Space qualified manufacturing processes were applied to manufacture and assemble the low noise amplifier module, and space qualification level of environment tests including thermal and vibration test were performed for it. The developed low noise amplifier was measured to show 30dB of minimum gain, $\pm$0.3dB of gain flatness, and 2.6dB of maximum noise figure over the desired operating frequency range from 30 to 31 GHz.

• Journal of the Korean Institute of Landscape Architecture
• /
• v.26 no.4
• /
• pp.82-94
• /
• 1999

According to Korean's geographical features of Taek Li Ji, the best location for human settlements is on the vicinity of a stream among a stream, an river and a sea, and not far from a ridge. The researcher chose one of best village which is called Yougokmaeul in Bonghwa-Gun, Kyungsang-Do. This village was created a gathering village with the same surname, can be translated as a hen and the front mountain can be seen as a rooster in the view of the shape of geographical features. As it were, the shape of this village and the cultivated land seems to be an egg inside a nest of a parent's chicken in the respect of the analogy of the theory of P'ungsuchiri which is known as Feng Shui in China and geomancy in the western world, and to effect the defensive psychology of the living environment in the terrain inland. This village is the studying place, Suckchunjungsa as the lecturing and studying place for their following students within the Chunghadonchun, the studying Yougok village, and even the ritual place performing ancestral sacrifices and the first incoming ancestor's graves in the same geographical system. The house site of the first incoming resident is surrounded the countian and is located in the front of Backsulryount which is the main mountain through Moonsu-san in the branch mountain of Korean's mountain system. Backsulryoung which is to be seen as the white peak, is symbolized the head of a hen which is to relate to a mysterious turtle in the view of P'ungsuchiri. And the pavilion which is called Chungamjung is sited on the rock of a shape of turtle which is symbolized to live longer. In the section of the mountain and water, Lee Jung Hwan mentioned a living place near the mountain stream is the best residential area and a landscape which is composed by a stream between mountains make a pleasure spirit and a bright feeling and make a refined person. If one can reach in the graceful mountain make a pleasure split and a bright feeling and make a refined person. If one can reach in the graceful mountain half day away, this kind of place must be a best living residential area to live. But this village was structured all in one place. And one of the ideas tangibly reflected in traditional Korean society's view of life and nature is the seclusion based on the Taoism. This kind of a dreamy thoughts make a dream to keep the paradise in our ancestors' mind. This kind of utopia is Chunghadonchun which is structured 5 aspects from the utopian gate near the Samgaesuewon to the village. These 5aspects is expressed by some Confucian thoughts as a small cosmos individually. On the third aspects which is the center among these aspects, the Suckchunjungsa which was made a seclusion place to devoting himself to his studies with refined tastes. The word of Jiju-am, Gangpung-dae, Jaewol-dae and Biryoung-pock are all expressed to cultivate one's moral character and to seek the truth by the Confucius'theory through the nature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.169-169
• /
• 2008

To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.