• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.685-689
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• 2005

In this paper, we consider a robust output feedback model predictive controller(MPC) design for Wiener model. Nonlinearities that couldn't be represented in static nonlinearity block of Wiener model are regarded as uncertainties in linear block. An dynamic output feedback controller design method is presented for Wiener MPC. According to MPC algorithm, the control law is computed based on linear matrix inequality(LMI)at each sampling time by solving convex optimization. Also, a new parameter dependent Lyapunov function is proposed to get a less conservative condition. The results are illustrated with numerical example.

• Journal of KSNVE
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• v.7 no.5
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• pp.847-852
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• 1997

Many investigations about the dynamic analysis of the structural system based on the BBA(Building Block Approach) method which predict dynamic characteristics of synthesized structures from each structure. But it is actually sometimes difficult to remove mounts from structures. In this paper, TFSM(The Transfer Function Separation Method) is developed which can predict dynamic characteristics of separated structures from the data of vibrational experiment of the synthesized structures. By combining TFSM with BBA, this paper also proposes the method which can predict dynamic characteristics of mount-modified structure without removing mounts from structures. And the proposed method is verified by the experimental data of plates.

• Proceedings of the Korean Reliability Society Conference
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• 2000.04a
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• pp.223-230
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• 2000

This work aims to develop modeling methodology of machine part reliability. The reliability model is to be used for predicting and improving reliability in planning and design processes of products. In order to develop the reliability model of machine parts, the functions and interactions of sub-units of machine parts are analyzed first and function network is constructed. Using the function network, function block diagram is developed, which can be the basis for deriving reliability block diagram. Modeling of machine part reliability has not been widely studied since the reliability modeling of machine parts requires understanding of the functions and failures of their components in several viewpoints. This work tries to find general methodology of reliability modeling and proposes a framework for reliability improvement during machine part development.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6A
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• pp.794-801
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• 2000

In this paper, the efficient new performance evaluation method for digital communication channels is suggested and verified its efficiency in terms of simulation run-tim for the digital satellite broadcasting satellite TV channel. In order to solve the difficulties of the existing Importance Sampling(IS) Technics, we adopted the discrete probability mass function(PMF) in the new method for estimating the statistical characteristics of received signals from the measured Nth order central moments. From the discrete probability mass function obtained with less number of the received signal than the one required in the IS technic, continuous cumulative probability function and its inverse function are exactly estimated by using interpolation and extrapolation technic. And the overall channel is simplified with encoding block, inner channel performance degra-dation modeing block which is modeled with the Uniform Random Number Generator (URNG) and concatenated Inverse Cummulative Pr bility Distribution function, and decoding block. With the simplified channel model, the overall performance evaluation can be done within a drastically reduced time. The simulation results applied to the nonlinear digital satellite broadcasting TV channel showed the great efficiency of the alogrithm in the sense of computer run time, and demonstrated that the existing problems of IS for the nonlinear satellite channels with coding and M-dimensional memory can be completely solved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.1
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• pp.70-78
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• 2019

In this paper, modeling of a high-resolution multi-function radar is proposed to simulate radar performance in a war game simulator, called AddSIM. To incorporate the multi-function radar model into the AddSIM, the modeling must comprise a component-based structure consisting of physics, logics, and information blocks. Therefore, we assign the RF hardware of a RADAR as the physic block, a controller as the logics block, and the RF specifications of the RADAR as the information block. Detailed modeling of the physics and logics blocks are addressed, and data structure is also presented on an engineering level. On a multi-target engaged scenario, the performance of the multi-function radar is numerically analyzed and its validation is examined.

• Journal of KIISE:Software and Applications
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• v.35 no.3
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• pp.149-161
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• 2008

As Programmable Logic Controllers(PLCs) are frequently used to implement real-time safety critical software, testing of PLC software is getting more important. We propose a structural testing technique on Function Block Diagram(FBD) which is one of the PLC programming languages. In order to test FBD networks, we define templates for function blocks including timer function blocks and propose an algorithm based on the templates to transform a unit FBD into a flowgraph. We generate test cases by applying existing testing techniques to the generated flowgraph. While the existing FBD testing technique do not consider infernal structure of FBD to generate test cases and can be applied only to FBD from which the specific intermediate model can be generated, this approach has advantages of systematic test case generation considering infernal structure of FBD and applicability to any FBD without regard to its intermediate format. Especially, the proposed method enables FBD networks including timer function blocks to be tested thoroughly. To demonstrate the effectiveness of the proposed method, we use trip logic of bistable processor of digital nuclear power plant protection systems which is being developed in Korea.

• Physical Therapy Korea
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• v.3 no.3
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• pp.44-58
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• 1996

The purpose of this study was to compare and evaluate various hand functions in the most common position (chair sitting, standing, floor sitting) used by cerebral palsied children with spastic diplegia. The results, analysed statistically, could be useful in suggesting treatment strategy for the improvement of hand function in such patient. For this study, 27 children mild or moderate spastic diplegia were chosen. They were patients of the Rehabilitation Hospital, Yonsei University Medical Center. Both dominant and nondominant hands were tested by the Box and Block Test. Bilateral hand function was tested by bead striding and card sorting activities. Collected data was analysed using univariate correlation analysis and MANOVA. Results were as follows: 1) In chair sitting there was a significant positive correlation between dominant hand scores in the Bloc and Box Test and chronological age, gestation period, and time of treatment initiation. In bilateral hand function, card sorting scores correlated positively with time of treatment initiation. 2) In standing, there was a significantly positive correlation between dominant hand scores in the Block and Box Test and time of treatment initiation. 3) In floor sitting, there was a significantly positive correlation between the dominance hand scores in the Block and Box Test and the tine of treatment initiation. Bead stringing, a bilateral hand activity, correlated positively with gestation period and birth weight but negatively with the postnatal incubation period. 4) That score of children who walked showed no significant difference in any of the three postures. 5) Highest test scores in children who could nat walk were in the Box and Block Test for nondominant hand in bead stringing for bilateral hand function. There scores occurred with the children in thee chair sitting posture. The results showed that, in order to improve hand function in children with spastic diplegia, it is necessary to maintain a well supported upright trunk posture with variations allowed for relevance to the chosen position of thee improvements hand activity being performed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1282-1287
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• 2002

In this Paper, we present the design of 10Mbps HomePNA(Home Phoneline Networking Alliance) PHY which is Home Network Technology using phone-line. It is connected with external interface through MII(Media Independent Interface) and AFE(Analog Front End) Interface. 10Mbps HomePNA PHY is composed with Management Block IEEE 802.3 CSMA/CD MAC(Media Access Control) Block Modulator block and Demodulator block. For their verification, we designed a prototype FPGA PCB board using XPC860T made in Motorola. We verified HomePNA frame data transmission using a driver program based Linux kernel. we verified rate negotiation by HomepNA 2.0 Link Layer Protocol.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.2
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• pp.73-78
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• 2004

By modeling the block matching algorithm as a function of the correlation of image blocks, we derive search patterns for fast block matching motion estimation. The proposed approach provides an analytical support lot the diamond-shape search pattern, which is widely used in fast block matching algorithms. We also propose a new fast motion estimation algorithm using adaptive search patterns and statistical properties of the object displacement. In order to select an appropriate search pattern, we exploit the relationship between the motion vector and the block differences. By changing the search pattern adaptively, we improve motion prediction accuracy while reducing required computational complexity compared to other fast block matching algorithms.

• Journal of the Korea Society of Computer and Information
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• v.22 no.5
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• pp.1-9
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• 2017

Recently, flash memory has been in a great demand from embedded system sectors for storage devices. However, program/erase (P/E) cycles per block are limited on flash memory. For the limited number of P/E cycles, many wear leveling techniques are studied. They prolonged the life time of flash memory using information tables. As one of the techniques, block erase table (BET) method using a bit array table was studied for embedded devices. However, it has a disadvantage in that performance of wear leveling is sharply low, when the consumption of memory is reduced. To solve this problem, we propose a novel wear leveling technique using Sampling-based Block Erase Table (SBET). SBET relates one bit of the bit array table to each block by using exclusive OR operation with round robin function. Accordingly, SBET enhances accuracy of cold block information and can prevent to decrease the performance of wear leveling. In our experiment, SBET prolongs life time of flash memory by up to 88%, compared with previous techniques which use a bit array table.