• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• 전자공학회논문지C
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• 제35C권12호
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• pp.49-58
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• 1998

본 논문에서는 무고정 부분 스캔 테스트 방법을 위한 새로운 스캔 선택 알고리즘에 대하여 논한다. 무고정 부분 스캔 테스트 방법은 모든 플립-플롭을 스캔하지 않는다는 점을 제외하면 완전 스캔과 동일한 테스트 방법이다. 이 테스트 방법은 테스트 벡터를 입력, 인가, 혹은 적용 등, 어느 때에도 스캔, 비스캔 중 어느 플립-플롭의 데이터 값도 고정하지 않는다. 제안된 스캔 선택 알고리즘은 무고정 부분 스캔 테스트 방법에서 완전 스캔 고장 검출율을 거의 유지하면서 많은 플립-플롭을 스캔하지 않게 한다.

• 전자공학회논문지C
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• 제35C권3호
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• pp.1-15
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• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• The Journal of Advanced Prosthodontics
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• 제14권2호
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• pp.88-95
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• 2022

PURPOSE. This study investigated the accuracy of full-arch intraoral scans obtained by various scan strategies with the segmental scan and merge methods. MATERIALS AND METHODS. Seventy intraoral scans (seven scans per group) were performed using 10 scan strategies that differed in the segmental scan (1, 2, or 3 segments) and the scanning motion (straight, zigzag, or combined). The three-dimensional (3D) geometric accuracy of scan images was evaluated by comparison with a reference image in an image analysis software program, in terms of the arch shape discrepancies. Measurement parameters were the intermolar distance, interpremolar distance, anteroposterior distance, and global surface deviation. One-way analysis of variance and Tukey honestly significance difference post hoc tests were carried out to compare differences among the scan strategy groups (α = .05). RESULTS. The linear discrepancy values of intraoral scans were not different among scan strategies performed with the single scan and segmental scan methods. In general, differences in the scan motion did not show different accuracies, except for the intermolar distance measured under the scan conditions of a 3-segmental scan and zigzag motion. The global surface deviations were not different among all scan strategies. CONCLUSION. The segmental scan and merge methods using two scan parts appear to be reliable as an alternative to the single scan method for full-arch intraoral scans. When three segmental scans are involved, the accuracy of complete arch scan can be negatively affected.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권7호
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• 한국산학기술학회논문지
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• 제14권9호
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• pp.4467-4471
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• 2013

본 연구에서는 Nano급 반도체 생산공정에서 필수적인 스피너(spinner) 설비의 감광액 도포(photo resist coating)시스템의 효율을 획기적으로 개선할 수 있는 새로운 완전스캔(Full-scan) 방식의 감광액 도포시스템(FPCS : Full-scan Photo-resist Coating System)을 개발하였다. 또한, 감광액의 미 도포로 인한 복합적인 공정불량을 예방하기 위하여 실시간(real-time)으로 상태요소들을 감시할 뿐만 아니라 상태요소의 비정상적 변화나 웨이퍼 가공불량이 발생할 경우 해당 유니트(unit)를 정지시킴과 동시에 원격지에 있는 엔지니어에게 경보를 전송함으로써 즉각적인 대처가 가능할 수 있도록 개발하였다.

• 한국자기학회지
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• 제26권3호
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• pp.92-98
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• 2016

신호증강효과기법을 이용한 자기공명혈관술에서 뇌동맥을 half scan factor에 따른 절반스캔과 완전스캔의 영상을 평가하는데 목적으로 한다. 뇌혈관성 질환이 없는 환자(n = 30)를 대상으로 절반스캔과 완전스캔 하였고, 뇌동맥의 관심영역을 세 영역(C1, C2, C3)에서 7~8 mm의 범위로 설정하였다. MIP로 재구성한 영상으로 신호강도를 SNR(signal to noise ration), PSNR(peak signal noise to ratio), RMSE(root mean square error), MAE(mean absolute error)을 산출하고 paired t-test를 이용하여 통계분석 하였다. 스캔시간은 절반스캔(4분 53초), 완전스캔(6분 04초)이었다. 뇌혈관의 모든 ROI의 평균 측정 범위(7.21 mm)이었고, 첫번째 C1의 SNR은 완전스캔(58.66 dB), 절반스캔(62.10 dB)이었고, 양의 상관관계($r^2=0.503$)이고, 두 번째 C2의 SNR은 완전스캔(70.30 dB), 절반스캔(74.67 dB)이고 양의 상관관계($r^2=0.575$)이었다. 세 번째 C3의 완전스캔 SNR(70.33 dB), 절반스캔 SNR (74.64 dB)로 양의 상관관계를 ($r^2=0.523$)로 분석되었다. 절반스캔과 완전스캔의 비교에서 SNR($4.75{\pm}0.26dB$), PSNR($21.87{\pm}0.28dB$), RMSE($48.88{\pm}1.61$)이었고 MAE($25.56{\pm}2.2$)로 산출되었다. SNR은 두 검사 스캔에서 통계학적으로 유의하지 않았고 (p-value > .05) 영상의 질에서는 많은 차이가 없어 완전스캔을 사용하였을 때보다 적은 시간이 소요되는 절반스캔을 적용하여 검사하여도 된다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.1097-1100
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• 1999

Due to the significant computation of full search in motion estimation, extensive research in fast motion estimation algorithms has been carried out. However, most of the algorithms have the degradation in predicted images compared with the full search algorithm. To reduce an amount of significant computation while keeping the same prediction quality of the full search, we propose a fast block-matching algorithm based on gradient magnitude of reference block without any degradation of predicted image. By using Taylor series expansion, we show that the block matching errors between reference block and candidate block are proportional to the gradient magnitude of matching block. With the derived result, we propose fast full search algorithm with adaptively determined scan direction in the block matching. Experimentally, our proposed algorithm is very efficient in terms of computational speedup and has the smallest computation among all the conventional full search algorithms. Therefore, our algorithm is useful in VLSI implementation of video encoder requiring real-time application.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• 인터넷정보학회논문지
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• 제4권3호
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• pp.31-37
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• 2003

본 논문에서는 유한상태머신을 위한 효율적인 비주사 DFT (design-for-testability) 기법을 제안한다. 제안된 기법은 순차회로 모델이 아닌 조합회로 모델을 사용한 ATPG를 수행하여 짧은 테스트 패턴 생성 시간과 완벽한 고장 효율을 보장한다. 또한 완전주사 기법이나 다른 비주사 DFT 기법에 비해 적은 면적 오버헤드를 보이며 테스트 패턴을 칩의 동작속도로 인가한다는 장점이 있다. 실험결과에서는 MCNC`91 벤치마크 회로를 이용하여 제안된 기법의 효율성을 입증한다.