• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.49-58
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• 1998

In this paper, we report new algorithms to select scan flip-flops for the no holding partial scan test method. The no holding partial scan test method is identical to the full scan test method except that some flip-flops are left unscanned. This test method does not hold scanned or unscanned flip-flops while shifting in test vectors, or applying them, or shifting out test results. The proposed algorithm allows a large number of flip-flops to be left unscanned while maintaining almost the complete full scan fault coverage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.1-15
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• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• The Journal of Advanced Prosthodontics
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• v.14 no.2
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• pp.88-95
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• 2022

PURPOSE. This study investigated the accuracy of full-arch intraoral scans obtained by various scan strategies with the segmental scan and merge methods. MATERIALS AND METHODS. Seventy intraoral scans (seven scans per group) were performed using 10 scan strategies that differed in the segmental scan (1, 2, or 3 segments) and the scanning motion (straight, zigzag, or combined). The three-dimensional (3D) geometric accuracy of scan images was evaluated by comparison with a reference image in an image analysis software program, in terms of the arch shape discrepancies. Measurement parameters were the intermolar distance, interpremolar distance, anteroposterior distance, and global surface deviation. One-way analysis of variance and Tukey honestly significance difference post hoc tests were carried out to compare differences among the scan strategy groups (α = .05). RESULTS. The linear discrepancy values of intraoral scans were not different among scan strategies performed with the single scan and segmental scan methods. In general, differences in the scan motion did not show different accuracies, except for the intermolar distance measured under the scan conditions of a 3-segmental scan and zigzag motion. The global surface deviations were not different among all scan strategies. CONCLUSION. The segmental scan and merge methods using two scan parts appear to be reliable as an alternative to the single scan method for full-arch intraoral scans. When three segmental scans are involved, the accuracy of complete arch scan can be negatively affected.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.9
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• pp.4467-4471
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• 2013

In this research, developed full-scan photoresist coating system(FPCS) can improve the efficiency of the photoresist coating system essential for spinner equipment in nano semiconductor manufacturing process. The devices developed in this research, which can be swiftly replaced in case abnormal state element changes or wafer manufacturing defect occurs, are anticipated to improve module yield as well as real-time monitoring on the state element in order to prevent the complex process defect due to the photoresist miss coating.

• Journal of the Korean Magnetics Society
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• v.26 no.3
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• pp.92-98
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• 2016

To aim of this study was to assess the full scan and half scan of imaging with half scan factor. Patients without a cerebral vascular disease (n = 30) and were subject to the full scan half scan, and set a region of interest in the cerebral artery from the three regions (C1, C2, C3) in the range of 7 to 8 mm. MIP (maximum intensity projection) to reconstruct the images in signal strength SNR (signal to noise ration), PSNR (peak signal noise to ratio), RMSE (root mean square error), MAE (mean absolute error) and calculated by paired t-test for use by statistics were analyzed. Scan time was half scan (4 minutes 53 seconds), the full scan (6 minutes 04 seconds). The mean measurement range (7.21 mm) of all the ROI in the brain blood vessel, was the SNR of the first C1 is completely scanned (58.66 dB), half-scan (62.10 dB), a positive correlation ($r^2=0.503$), for the second C2 SNR is completely scanned (70.30 dB), half-scan (74.67 dB) the amount of correlation ($r^2=0.575$), third C3 of a complete scan SNR (70.33 dB), half scan SNR (74.64 dB) in the amount of correlation between the It was analyzed with ($r^2=0.523$). Comparative full scan with half of SNR ($4.75{\pm}0.26dB$), PSNR ($21.87{\pm}0.28dB$), RMSE ($48.88{\pm}1.61$), was calculated as MAE ($25.56{\pm}2.2$). SNR is also applied to examine the half-scans are not many differences in the quality of the two scan methods were not statistically significant in the scan (p-value > .05) image takes less time than a full scan was used.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1097-1100
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• 1999

Due to the significant computation of full search in motion estimation, extensive research in fast motion estimation algorithms has been carried out. However, most of the algorithms have the degradation in predicted images compared with the full search algorithm. To reduce an amount of significant computation while keeping the same prediction quality of the full search, we propose a fast block-matching algorithm based on gradient magnitude of reference block without any degradation of predicted image. By using Taylor series expansion, we show that the block matching errors between reference block and candidate block are proportional to the gradient magnitude of matching block. With the derived result, we propose fast full search algorithm with adaptively determined scan direction in the block matching. Experimentally, our proposed algorithm is very efficient in terms of computational speedup and has the smallest computation among all the conventional full search algorithms. Therefore, our algorithm is useful in VLSI implementation of video encoder requiring real-time application.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of Internet Computing and Services
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• v.4 no.3
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• pp.31-37
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for finite state machine(FSM) is proposed. The proposed method always guarantees short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The efficiency of the proposed method is demonstrated using well-known MCNC'91 FSM benchmark circuits.