• 대한전자공학회논문지SD
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• 제47권6호
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• pp.7-12
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• 2010

유기물 쇼트기 다이오드 회로 설계시에 사용가능한 소자의 모델을 구현하였다. AHDL을 이용하여 상용 CAD 환경으로 보편적으로 사용되는 Spectre의 설계환경에서 측정 결과를 입력 파라미터로 반영하여 회로 시뮬레이션을 할 수 있는 환경을 구성하였다. 유기물 RFID의 구현에 필수적인 정류회로를 제작하여 회로의 주파수 특성을 측정하였으며, AHDL 모델을 사용한 시뮬레이션 결과와 비교하였다. 제작된 정류회로의 주파수 특성은 13.56MHz의 RFID 동작을 만족시키기에는 부족하지만, 135kHz 주파수 대역 RFID에서는 동작이 가능하다.

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.89-96
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• 2002

본 논문은 ELA알고리듬의 수평방향 및 수직방향과 대각선 방향을 판단하여 수평 윤곽선 및 수직 윤곽선 특성을 시각적인 면과 객관적인 면에서 개선한 ADI(adaptive de-interlacing)알고리듬을 제안하고, 제안한 알고리듬에 대한 수직을 전개, 이를 C, Matlab을 이용하여 검증하였다. 제안한 알고리듬의 구조를 $0.6{\mu}m$ 2-poly 3-metal CMOS 표준 라이브러리를 적용하고 Cadence툴을 이용하여 회로 및 논리 시뮬레이션을 수행하고 레이아웃을 작성하였다.

• ETRI Journal
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• 제31권4호
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• pp.478-480
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• 2009

The design of a CMOS clamped-clamped beam resonator along with a full custom integrated differential amplifier, monolithically fabricated with a commercial 0.35 ${\mu}m$ CMOS technology, is presented. The implemented amplifier, which minimizes the negative effect of the parasitic capacitance, enhances the electrical MEMS characterization, obtaining a $48{\times}10^8$ resonant frequency-quality factor product ($Q{\times}f_{res}$) in air conditions, which is quite competitive in comparison with existing CMOS-MEMS resonators.

• International Journal of CAD/CAM
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• 제6권1호
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• pp.173-181
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• 2006

In this paper, an integration framework of Geometric Constraint Solving Engine and AutoCAD is presented, and a dynamic geometric constraint system is introduced. According to inherent orientation features of geometric entities and various Object Snap results of AutoCAD, the' proposed system can automatically construct an under-constrained geometric constraint model during interactive drawing. And then the directed constraint graph in a geometric constraint model is realtime modified in order to produce an optimal constraint solving sequence. Due to the open object-oriented characteristics of AutoCAD, a set of user-defined entities including basic geometric elements and graphics constraint relations are defined through derivation. And the custom-made Object Reactor and Command Reactor are also constructed. Several powerful characteristics are achieved based on these user-defined entities and reactors, including synchronously processing geometric constraint information while saving and opening DWG files, visual constraint relations, and full adaptability to Undo/Redo operations. These characteristics of the proposed system can help the designers more easily manage geometric entities and constraint relations between them.

• 한국의류산업학회지
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• 제19권4호
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• pp.411-420
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• 2017

With the increasing popularization of low-priced luxury markets, maintaining the genuine values of luxury has become crucial for luxury fashion brands to attract customers who want exclusivity and rarity. The world-leading luxury fashion houses have employed a variety of experiential marketing strategies like special order product strategies and mobile SNS promotion strategies, yet little research exists on there the strategies actually positively impact brand luxury images and customer attitudes towards the brand. This study empirically analyzed the effects of customer experience of special order products on perceived brand luxury and brand relationship. Furthermore, the study also tested relationships among perceived brand luxury, brand relationship, and brand loyalty. A survey was conducted with Korean female consumers who had purchase experiences of special order products from the brands. We analyzed the data of MTO-experienced respondents due to the lack of respondents who had experienced custom-made product services. The result indicates the significant effect of experience of MTO on brand relationship; however, we found only a partial support for the effect of MTO on brand luxury. Likewise, we found a partial support for the effect of mobile SNS promotion strategies on perceived brand luxury versus full support for the effect on brand relationship.

• 한국통신학회논문지
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• 제23권7호
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• pp.1718-1731
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• 1998

디지탈 quadrature 복조기는 디지탈 통신 시스템에서 변조된 신호의 정확한 위상 복조를 위해 꼭 필요하다. 기존의 방법들은 주로 DDFS(Direct Digital Frequency Synthsizer)를 이용하여 캐리어를 발생시킨 후에 승산기를 이용하여 복조를 수행하였다. 그리고, DDFS에는 주로 ROM(Read Only Memory)을 사용하였는데, 높은 속도와 정확도를 요구하는 경우 ROM의 속도와 크기가 제한이 될 수있다. 이러한 점을 극복하기 위하여 CORDIC(COordinate Rotation Digital Computer) 알고리듬을 사용하여 주파수 합성은 물론 캐리어 복조까지 수행하는 방식을 제안하였다. 최적의 하드웨어 구현을 위해 제한된 단어길이에 의한 영향을 분석하였으며, 하드웨어 비용면에서 ROM을 사용하는 방법과 비교한 결과 약 1/3 정도로 면적이 줄었다. 제안된 구조를 이요한 전주문형 VLSI 구현 결과를 보인다.

• 한국통신학회논문지
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• 제28권11A호
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• pp.929-935
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• 2003

ATM 교환기 망동기용 아날로그/디지털 혼합형 ASIC을 설계 제작하였다. 이 ASIC은 상대 시스템으로부터 전송되어온 46.94 MHz의 클럭을 이용하여 234.7/46.94 MHz의 시스템용 클럭 및 77.76/19.44 MHz의 가입자용 클럭을 발생시키는 역할을 하며, 전송된 클럭의 체크 및 선택 기능도 동시에 포함한다. 효율적인 ASIC 구성을 위하여 고속 클럭 발생을 위한 2개의 아날로그 PLL 회로는 전주문 방식으로, 외부 입력 클럭 체크 및 선택을 위한 디지털 회로는 표준 셀 방식으로 설계하였다. 또한, 아날로그 부분에는 일반 CMOS 공정으로 제작 가능한 저항 및 커패시터를 사용함으로서 0.8$\mu\textrm{m}$ 디지털 CMOS 공정으로 칩을 제작 가능케 하여 제작비용도 줄였다. 제작된 칩을 측정한 결과 234.7 MHz 및 19.44 MHz의 안정된 클럭을 발생하였으며, 클럭의 실효 지터도 각각 4 ㎰ 및 17 ㎰정도로 낮게 나타났다.

• 정보학연구
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• 제6권4호
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• pp.11-23
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• 2003

본 논문에서는 캐리 전파가 없어 고속연산이 가능한 잉여수계를 이용하여 생산자동화 시스템에서 실시간 물체인식을 위한 디지털 뉴런프로세서의 구현방법을 제안하였다. 설계된 디지털 뉴런프로세서는 잉여수계를 이용한 MAC 연산기와 혼합계수 변환을 이용한 시그모이드 함수 연산부로 구성되며, 설계된 회로는 C언어 및 VHDL로 기술하였고 Compass 툴로 합성하였다. 최종적으로, LG 0.8${\mu}m$ CMOS 공정을 사용하여 Full Custom방식으로 설계를 수행하였다. 실험결과, 가장 나쁜 경로일 경우, 약 19nsec의 지연속도와 0.6ns의 연산속도를 보였고, 기존의 실수 연산기에 비하여 약 1/2배정도 하드웨어 크기를 줄일 수 있었다. 본 논문에서 설계한 디지털 뉴런프로세서는 실시간 처리를 요하는 생산자동화 시스템의 물체인식 시스템에 적용될 수 있을 것으로 기대된다.

• 대한전자공학회논문지SD
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• 제44권12호
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• pp.54-60
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• 2007

본 논문에서는 내장메모리의 고장을 효율적으로 치유하기 위해 2차원의 여분 메모리를 이용한 내장메모리의 자가치유회로를 제안한다. 내장메모리에 같은 행(열)에 다수의 고장이 발생할 경우에 기존의 1차원의 여분 열(행) 메모리를 이용할 경우에는 고장 수만큼의 여분 메모리 열(행)이 필요하나. 2차원의 메모리를 사용하는 본 방법에서는 하나의 여분 메모리 행(열)으로 치유가 가능하다. 또한, 가상분할 메모리방식을 이용함으로써 여분 메모리 열 전체가 아니라 부분 열을 이용하여 치유가 가능하다. 본 구조를 이용하여, $64\times1$ bit의 코어메모리와 $2\times8$의 2차원 여분 메모리로 구성된 자가치유회로를 설계한다. 그리고, 고장검출을 위해서 13N March 알고리즘을 가진 자가테스트회로를 내장한다. 매그너칩 $0.25{\mu}m$ CMOS공정을 이용하여 Full-Custom으로 설계한 결과, 10,658개의 Tr.수에 코어면적은 $1.1\times0.7mm^2$이 소요되었다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}