• 대한전자공학회논문지TC
• /
• 제47권1호
• /
• pp.84-90
• /
• 2010

본 논문에서는 주파수 조절 범위의 감소 없이 위상 잡음을 줄이고 회로 크기를 최소화하기 위하여 혼합 우좌향 전송 선로 기반의 고조파 조절 회로를 이용한 새로운 전압 제어 발진기를 제안하였다. 위상 잡음은 2차와 3차 고조파에서 동시에 단락임피던스를 갖는 새로운 고조파 조절 회로에 의해 줄어들었다. 제안된 고조파 조절 회로는 혼합 우좌향 전송 선로의 주파수 오프셋과 위상 기울기에 의한 이중 대역 특성을 갖는 혼합 우좌향 전송 선로를 이용하여 설계되었다. 높은 Q 특성의 공진기는 위상 잡음을 줄이기 위하여 사용되어 왔지만, 주파수 조절 범위가 감소하는 문제를 갖고 있다. 하지만 제안된 전압 제어 발진기의 주파수 조절 범위는 위상 잡음이 높은 Q 특성의 공진기 없이 감소하였기 때문에 줄어들지 않았다. 또한, 일반적인 우향 전송 선로 대신 혼합 우좌향 전송 선로를 이용하는 것을 통하여 회로의 크기를 소형화 하였다. 전압 제어 발진기의 위상 잡음은 5.731 ~ 5.938 GHz의 주파수 조절 범위 내에서 100 kHz의 오프셋 주파수에서 -119.17 ~ -117.50 dBc/Hz이다.

• 한국전자파학회:학술대회논문집
• /
• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
• /
• pp.234-238
• /
• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.

• 대한전자공학회논문지SD
• /
• 제47권2호
• /
• pp.87-93
• /
• 2010

이 글은 공정, 전압, 온도 변화를 극복하기 위한 2단계 자동 트랜스컨덕턴스 조절 기능을 가진 저전력, 광대역 전압제어발진기의 설계에 관한 논문이다. 광대역에서 전압제어발진기를 발진시키기 위해, 디지털 자동 트랜스컨덕턴스 조절 루프와 아날로그 자동 진폭조절 루프가 사용되었다. 전압제어발진기의 출력 스윙 크기에 따라 트랜지스터의 바디전압을 조절하는 기능도 저전력 구현을 위해 설계되었다. 소모전류는 1.2 V 공급전압에서 2 mA에서 6 mA까지 1 mA 단위로 조절된다. 전압제어발진기의 튜닝 범위는 2.35 GHz에서 5 GHz까지 2.65 GHz로써 72%이다. 위상잡음은 중심주파수 3.2 GHz를 기준으로 1MHz 떨어진 지점에서 -117 dBc/Hz 이다.

• ETRI Journal
• /
• 제33권3호
• /
• pp.366-373
• /
• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• 대한전자공학회논문지SD
• /
• 제48권3호
• /
• pp.34-41
• /
• 2011

본 논문은 넓은 튜닝 범위와 정밀한 해상도 성능을 가지는 능동 인덕터를 이용한 디지털 제어 발진기에 대한 논문이다. 디지털 제어 발진기의 주파수를 조정하기 위해 능동 인덕터의 트랜스컨덕턴스를 디지털적으로 조정하는 구조를 제안하였으며, 디지털 제어 발진기의 이득 또한 디지털적으로 조정하여 이득 변화를 상쇄하도록 하였다. 또한, 넓은 튜닝 영역과 정밀한 해상도를 구현하기 위해 자동 3 단계 주파수 및 이득 튜닝 루프를 제안하였다. 디지털 제어 발진기의 총 주파수 튜닝 영역은 2.1 GHz ~ 3.5 GHz로 1.4 GHz의 영역으로 이는 2.4 GHz의 중간 주파수에 대하여 58 %에 해당한다. 유효 주파수 해상도는 시그마 델타 모듈레이터를 사용하여 0.14 kHz/LSB를 구현하였다. 제안하는 디지털 제어 발진기는 0.13 ${\mu}m$ CMOS 공정으로 설계 되었다. 전체전력 소모는 1.2 V 공급전압에서 6.6 mW이며 위상 잡음 성능은 2.4 GHz 중간 주파수의 경우, 1 MHz 오프셋에서 -120.67dBc/Hz 성능을 보이고 있다.

• 소음진동
• /
• 제3권2호
• /
• pp.137-143
• /
• 1993

The conventional dynamic vibration absorber is very efficient in inhibiting the vibration of a machine. This is accomplished by "tuning" the absorber to the frequency of the harmonic disturbing force. If, however, the frequency of the disturbing force varies over a tuning frequency range in the normal operation of the system, the linear dynamic absorber may become inoperative and might aggravate matters particularly. This study is to endow the dynamic absorber with greater flexibility in suppressing vibrations throught a range of frequencies of the disturbing force. By introducing springs with nonlinear characteristics into its design, the results can be obtained. In this paper, the machine and the absorber were modelled as a nonlinear two-degree-of freedom system. And the concepts of nonlinear normal mode were adopted to obtain this purpose.s purpose.

• Journal of Power Electronics
• /
• 제12권6호
• /
• pp.851-858
• /
• 2012

This paper presents resonant inverter tuning for current source parallel resonant induction heating systems based on a new self oscillating switching technique. The phase error is suppressed in a wide range of operating frequencies in comparison with Phase Locked Loop (PLL) techniques. The proposed switching method has the capability of tuning under fast changes in the resonant frequency. According to this switching method, a multi-frequency induction heating (IH) system is proposed by using a single inverter. In comparison with multi-level inverter based IH systems, the advantages of this technique are its simple structure, better transients and wide range of operating frequencies. A laboratory prototype was built with an operating frequency of 35 kHz to 55 kHz and 300 W of output power. The performance of the IH system shows the validity of the new switching technique.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 추계학술대회 논문집 전력기술부문
• /
• pp.38-40
• /
• 2003

This paper describes the integrated dynamic stability(IDS) program for tuning the power system controllers, such as PSS, AVR and so on. IDS consists of three modules; power flow module, PWRLF, to calculate large scale power system load flow solutions, IDS/PSS module to calculate eigenvalues and frequency response in the range of frequency from 0.2Hz to 2Hz, and IDS/NEA module to calculate eigenvalues in the range of frequency from 5.0Hz to 55Hz. In addition, IDS provides graphic user interface(GUI) in order to let the user handle and analyze the input data and the results of calculation with convenience.

• IEIE Transactions on Smart Processing and Computing
• /
• 제4권3호
• /
• pp.158-162
• /
• 2015

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

• Journal of electromagnetic engineering and science
• /
• 제5권1호
• /
• pp.8-13
• /
• 2005

The InGaP/GaAs hetero-junction bipolar transistor(HBT) monolithic voltage-controlled dielectric resonator oscillator(VCDRO) is first demonstrated for a Ku-band low noise block down-converter(LNB) system. The on-chip voltage control oscillator core employing base-collector(B-C) junction diodes is proposed for simpler frequency tuning and easy fabrication instead of the general off-chip varactor diodes. The fabricated VCDRO achieves a high output power of 6.45 to 5.31 dBm and a wide frequency tuning range of ]65 MHz( 1.53 $\%$) with a low phase noise of below -95dBc/Hz at 100 kHz offset and -115 dBc/Hz at ] MHz offset. A]so, the InGaP/GaAs HBT monolithic DRO with the same topology as the proposed VCDRO is fabricated to verify that the intrinsic low l/f noise of the HBT and the high Q of the DR contribute to the low phase noise performance. The fabricated DRO exhibits an output power of 1.33 dBm, and an extremely low phase noise of -109 dBc/Hz at 100 kHz and -131 dBc/Hz at ] MHz offset from the 10.75 GHz oscillation frequency.