• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.20-26
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• 2010

In this paper, a frequency tripler has been designed with 100mW medium-power using P-HEMT. It is designed to obtain 7.2 GHz frequency at the output that is an integer multiple of 2.4 GHz input frequency by using nonlinear device that produces 3rd harmonic. The frequency tripler is designed by using load-pull simulation. To suppress the 2nd and fundamental, notch filter is used for the frequency tripler. The tripler is designed to obtain about 21dBm output power with 15 dBm input, i.e., 6 dB conversion gain and the suppression of 20 dBc at fundamental, and 30 dBc at the second harmonics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.971-978
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• 2013

This work presents a W band frequency synthesizer which is composed of 26 GHz VCO, Phase Locked Loop and frequency tripler using 65 nm RF CMOS process. Frequency tuning range of 26 GHz VCO covers the band from 22.8~26.8 GHz and final output frequency of the tripler is from 74 to 75.6 GHz. The fabricated frequency synthesizer consumes 75.6 mW and its phase noise is -75 dBc/Hz at 1 MHz offset, -101 dBc/Hz 10 MHz offset respectively.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.47-52
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• 2010

In this paper, a frequency tripler has been designed with 100mW medium-power using P-HEMT. It is designed to obtain 7.2GHz frequency at the output that is an integer multiple of 2.4GHz input frequency by using nonlinear device that produces 3rd harmonic. The frequency tripler is designed by using load-pull simulation. To suppress the 2nd and fundamental, notch filter is used for the frequency tripler. The tripler is designed to obtain about 21dBm output power with 15dBm input, i.e., 6dB conversion gain and the suppression of 20dBc at fundamental, and 30dBc at the second harmonics.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.71-76
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• 2010

In this paper, a 120 GHz local oscillator(LO) for the sub-harmonic mixer in the THz transceiver with a carrier frequency of 240 GHz was designed and fabricated. A 120 GHz local oscillator was composed of 40 GHz PLL(Phase Locked Loop), 40 GHz BPF(Band Pass Filter), frequency tripler and 120 GHz BPF. The commercial model of the frequency tripler was used. The measured result of the 40 GHz PLL showed the phase noise of -105 dBc/Hz at the 100 kHz offset frequency. The measured result of 120 GHz BPF showed the insertion loss of 1.3 dB at center frequency of 119 GHz with bandwidth of 5 GHz. The output power of 120 GHz LO was measured to 6.6 dBm.

• Journal of electromagnetic engineering and science
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• v.6 no.2
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• pp.92-97
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• 2006

In this paper, a fully integrated Ku-band tripler differential MMIC voltage controlled oscillator(VCO), which consists of a differential VCO core and two triplers, is developed using high linearity InGaP/GaAs HBT technology. The VCO core generates an oscillation frequency of 3.583 GHz, an output power of 3.65 dBm, and a phase noise of -96.7 dBc/Hz at 100 kHz offset with a current consumption of 30 mA at a supply voltage of 2.9 V. The tripler shows excellent side band rejection of 23 dBc at 3 V and 12 mA. The tripler differential MMIC VCO produces an oscillation frequency of 10.75 GHz, an output power of -13 dBm and a phase noise of -89.35 dBc/Hz at 100 kHz offset.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.322-325
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• 2003

A 7/21GHz frequency tripler, using a commercially available packaged pHEMT, was designed and fabricated on 15mil RO3003 substrate. Frequency conversion is realized using the third harmonic current of an class B amplifier with rejection feedback at fundamental with optimum load conductance at the third harmonic. The fabricated frequency tripler has achieved a conversion loss of 0.7dB for an input power of 0dBm at 21GHz. The experimental results show good agreement with the harmonic balance simulation.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.247-251
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• 2001

본 논문에서는 MESFET을 이용하여 2670MHz에서 8010MHz로 주파수를 체배하는 Frequency Tripler를 설계 및 제작하였다. A급에 동작점을 두어 3차 하모닉 성분을 발생시켰고, λ$_{g}$/4 개방형 스터브와 대역통과 필터를 이용하여 기본주파수와 2차 하모닉성분을 억제하였다. 측정결과 0dBm의 입력신호에 대해 출력주파수인 8.16GHz에서 변환이득은 -0.33dB, -55dBc의 기본 주파수 억압, -33dBc의 2차 하모닉 성분의 억압을 얻었다. 2.5GHz～2.84GHz의 입력주파수에서 400MHz의 사용대역을 얻었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10A
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• pp.1031-1036
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• 2006

This paper proposes a novel BPF structure with less insertion loss and small size instead of the existing coupled line BPF for the output of the tripler using APDP (Anti-Parallel Diode Pair). This proposed BPF consists of the interdigital capacitor and spiral open stub. The proposed BPF has the insertion loss of less than 0.7dB within the band $(16.41{\sim}19.23GHz)$. The conversion loss of the tripler is about $16.6{\sim}18.5dB$ $(flatness<{\pm}1dB)$ at $5.72{\sim}6.28GHz$ of fundamental frequency. Its fundamental frequency and the fifth harmonic suppression characteristic at 6GHz are -32.16dBc and -44.6dBc, respectively And its phase noise attenuation characteristic is about 9.5dB at 100kHz.

• Journal of IKEEE
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• v.22 no.4
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• pp.1088-1092
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• 2018

In this paper, we propose a dual-mode frequency tripler using push-push and stacked FET structures. The proposed circuit can operate either in frequency multiplier mode or in amplifier mode. In the frequency multiplier mode, push-push frequency multiplication is achieved by allowing input signals with particular phase shifts. In the amplifier mode, the device operates as a distributed amplifier to obtain high gain. Also both modes were designed using stacked FET structure. The designed circuit showed frequency tripled output power of 9.7 dBm at 2.4 GHz with the input at 800 MHz. On the other hand, in the amplifier mode, the device showed 8.9 dB of gain to generate 19.5 dBm at 800 MHz.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.49-55
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• 2015

This paper proposes a 2.4 GHz RF oscillator with a very low close-in phase noise performance. This is composed of a low frequency crystal oscillator and three frequency multipliers such as two doubler (X2) and one tripler (X3). The proposed oscillator is implemented as a hybrid type circuit design using a discrete silicon bipolar transistor. The measurement results of the proposed oscillator structure show -115 dBc/Hz close-in phase noise at 10 kHz offset frequency, while only dissipating 5 mW from a 1-V supply. Its close-in phase noise level is very close to that of a low frequency crystal oscillator with little degradation of noise performance. The proposed structure which is consisted of a low frequency crystal oscillator and a frequency multiplier provides new method to implement a low power low close-in phase noise RF local oscillator.