• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.11
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• pp.98-102
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• 2011

This paper describes inverse E class frequency multiplier which is lower inductance and peak switching voltage than E class frequency multiplier. The frequency multiplier is designed to generate 5.8[GHz] frequency by doubling the input frequency 2.9[GHz]. The peak switching voltage of designed inverse E class frequency multiplier with 11[V] is lower 4[V] than that of E class frequency multiplier with 15[V]. The inverse E class frequency multiplier has a conversion gain 6[dB] at output power 21[dBm] and maximum 35[%] power efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.12
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• pp.1108-1111
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• 2015

In this paper, a ${\times}49$ frequency multiplier based on a ring oscillator and a multi-push multiplier is presented. The proposed ${\times}49$ frequency multiplier consists of two ${\times}7$ frequency multipliers and these multiplier is connected by injection-locking technique. Each ${\times}7$ frequency multiplier consists of a ring oscillator with 14-phase output signal and 7-push frequency multiplier requiring 14-phase input. The proposed ${\times}49$ frequency multiplier provides 2.78~2.83 GHz output signal with 56.7~57.7 MHz input signal. This operation frequency is defined that the output power difference between the carrier and the spur is above 10 dB. The proposed chip consumes 13.93 mW.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.846-853
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• 2009

This paper presents the design of a high efficiency frequency multiplier with load-pull simulation and analyses the nonlinear distortion of the frequency multiplier. The frequency multiplier shows serious distortion of multiplying signal bandwidth because of nonlinearity when modulated signal is applied, so a digital predistortion with look up table (LUT) is applied to compensate for the distortion of the frequency multiplier. The frequency multiplier is designed to produce 5.8GHz output by doubling the input frequency to be operating at IEEE 802.11a standard wireless LAN. The output spectrum shows 12dB ACPR improvement both at +11MHz, +20MHz offset from center frequency after linearization.

• Journal of Advanced Navigation Technology
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• v.10 no.4
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• pp.348-355
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• 2006

In this paper, frequency multipliers used S-band transponder of the KOMPSAT 3 are designed and fabricated. In the transponder, 108 times multiplier which generate 1st LO signal(2008.8MHz) is comprised of the X9 frequency multiplier, 1st X2 multiplier, 2nd X2 multiplier and the last stage of the X3 frequency multiplier. As results, output power of 8.17 dBm at 2008.8MHz, the harmonic suppression of -56.67dBc, the bandwidth of 14MHz were measured.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.10
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• pp.90-99
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• 2009

In this paper, we proposed the new class-E frequency multiplier design that include the highest efficient characteristics. The proposed frequency multiplier is designed for 5.8[GHz] output using the frequency multiplier about 2.9[GHz] input signal. And studying in this paper is for the design and the implementation of the class E frequency multiplier. For the result, the maximum highest efficient characteristics 32[%] which is with output power 24.5[dBm] and 8.5[dB], is shown with frequency multiplier for the 2.9/5.8[GHz] class E. And we applied the linear method to the implemented class E frequency multiplier. As a result, the output spectrum for the linear is upgrade to 12[dB], 12[dB], 13[dB] of the ACPR characteristics on the +11[MHz], +20[MHz], +30[MHz] offset frequency in the center frequency. The result is satisfied with the 3.83[%] of the lineared EVM for the 64-QAM modulated method with the 54[Mbps] transmission velocity. In this paper, we show that the good compensation result of the linearity and the efficiency through the digital pre-linear method of the distortion with the frequency multiplier. Therefore, we suggested the frequency multiplier method are applying to WLAN, cellular, PCS, WCDMA, and etc.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.391-396
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• 2010

This paper presents some important research result comparisons for multi function RF modules which use amplifier or frequency multiplier. By using multiplier, multi function module can be realized amply in comparison to multi band module which has separate block for each frequency band. Some com paring analysis among the switching method between separate amplifier and multiplier, the structure using frequency selective reflector, and the module using the defected ground structure. The multi function module which operates as amplifier or multiplier with input frequency is developed and input frequency suppression and output harmonics suppression can be improve d by using defected ground structure.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.148-153
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• 2011

In this paper, an inverse class E frequency multiplier has been designed to generate 5.8 GHz wireless LAN signal by multiplying 2.9 GHz input. The inverse class E frequency multiplier is operating with low inductance value and low peak drain voltage than the class E frequency multiplier. Measurement shows the output power of 21 dBm, the mutiplier gain of 6 dB, and the PAE(Power Added Efficiency) of 35 % with 15 dBm input power.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.1
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• pp.22-26
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• 1967

The efficiency of frequency multiplier using nonlinear elements varies with the characteristics of the elements and also varies with the order of multiplication. And, if the elements is resistive, the efficiency varies with reverse-to-forward resistance value. Microwave energy which was frequency doubled by a nonlinear resistive element was obtained, and the theoretical efficiency of nonlinear reactive and resistive multiplier were compared with the efficiency taken by experiments. It was found that efficiency of frequency multiplier using the nonlinear resistive elements was increased, without depending on frequency, with the reverse-to-forward resistance value.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.143-146
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• 2016

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.