• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.5
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• pp.522-527
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• 2011

In this work, a 54 GHz divide-by-3 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in a 0.13-${\mu}M$ Si RFCMOS technology for phase-locked loop(PLL) application. The free-running frequency is 18.92~19.31 GHz with tuning range of 0~1.8 V, consuming 70 mW with a 1.8 V supply voltage. At 0 dBm input power, the locking range is 1.02 GHz(54.82~55.84 GHz) and, with varactor tuning of 0~1.8 V, the total operating range is 2.4 GHz(54.82~57.17 GHz). The fabricated circuit size is 0.42 mm${\times}$0.6 mm including probing pads and 0.099 mm${\times}$0.056 mm for core area.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.233-236
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• 2005

Phase noise in a phase-locked-loop (PLL) is unwanted and unavoidable. It is a main concern in oscillation system especially PLL. The phase noise is derived in term of power spectrum density by using a reliable phase noise model. There are four noise sources being considered in this paper, which are generated by reference oscillator, voltage controlled oscillator, filter, and main divider. The major concern for this paper is the noise from the filter. Two types of second order low pass filter are used in the PLL system. Applying the mathematical phase noise model, the output noises are compared. The total noise from the passive filter is lower than the active filter at the offset frequency range between 1 Hz to 33 kHz.

• Journal of information and communication convergence engineering
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• v.9 no.3
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• pp.305-309
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• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Journal of IKEEE
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• v.19 no.2
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• pp.176-185
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• 2015

The study aims to a design hybrid frequency synthesizer in spectrum analyzer and to propose new techniques designed for evasion of in-band spurious. The study focuses on calculating the exact location of multiple phase locked loop of hybrid frequency synthesizer and spurious of direct digital synthesizer to evade in-band spurious outside of frequency range that the user wants to see and thereby simulating technique to improve input related spurious of spectrum analyzer for algorithm. The proposed technique is designed to calculate spurious evasion algorithm in central processing system when in-band spurious arises, and to move output frequency of DDS(direct digital synthesizer) into the place where no in-band spurious exists thereby improving performance of frequency synthesizer. The study used simulation and result representation to prove the effectiveness of the proposed technique.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.635-645
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• 2016

In this paper, we showed the phase noise of voltage controlled oscillator(VCO) can be radically improved using FLL(Frequency Locked Loop). At first, a 5 GHz VCO is fabricated using a hair-pin resonator. The fabricated VCO shows a phase noise of -53.1 dBc/Hz at 1 kHz frequency offset. In order to improve the phase noise of the fabricated VCO, a FLL is constructed using the feedback loop that consists of the VCO, a frequency detector composed of 5 GHz resonator, loop-filter, and level shifter. The fabricated FLL is designed to oscillate at a frequency of 5 GHz, and its measured phase noise is about -120.6 dBc/Hz at 1 kHz offset frequency. As a result, the phase noise of VCO can be radically improved by about 67.5 dB applying FLL. In addition, the measured phase noise performance is close to that of crystal oscillator.

• Journal of Communications and Networks
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• v.7 no.3
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• pp.248-257
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• 2005

In this paper, we develop design procedures for carrier tracking loop for orthogonal frequency division multiplexing (OFDM) systems or other systems of blocked data. In such communication systems, phase error measurements are made infrequent enough to invalidate the traditional loop design methodology which is based on analog loop design. We analyze the degradation in the OFDM schemes caused by the tracking loop and show how the performance is dependent on the rms phase error, where we distinguished between the effect of the variance in the average phase over the symbol and the effect of the phase change over the symbol. We derive the optimal tracking loop including optional delay in the loop caused by processing time. Our solution is general and includes arbitrary phase noise apd additive noise spectrums. In order to guarantee a well behaved solution, we have to check the design against margin constraints subject to uncertainties. In case the optimal loop does not meet the required margin constraints subjected to uncertainties, it is shown how to apply a method taken from control theory to find a controller. Alternatively, if we restrict the solution to first or second order loops, we give a simple loop design procedure which may be sufficient in many cases. Extensions of the method are shown for using both pilot symbols and data symbols in the OFDM receiver for phase tracking. We compare our results to other methods commonly used in OFDM receivers and we show that a large improvement can be gained.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• Journal of Power Electronics
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• v.15 no.1
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• pp.216-226
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• 2015

Grid synchronization is one of the key techniques for the grid-connected power converters used in distributed power generation systems. In order to achieve fast and accurate grid synchronization, a new phase locked loop (PLL) is proposed on the basis of the complex filter matrixes (CFM) orthogonal signal generator (OSG) crossing-decoupling method. By combining first-order complex filters with relation matrixes of positive and negative sequence voltage components, the OSG is designed to extract specific frequency orthogonal signals. Then, the OSG mathematical model is built in the frequency-domain and time-domain to analyze the spectral characteristics. Moreover, a crossing-decoupling method is suggested to decouple the fundamental voltage. From the eigenvalue analysis point of view, the stability and dynamic performance of the new PLL method is evaluated. Meanwhile, the digital implementation method is also provided. Finally, the effectiveness of the proposed method is verified by experiments under unbalanced and distorted grid voltage conditions.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1613-1616
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• 2008

A Transcutaneous Energy Transmission System (TET) has been developed for the wireless energy transmission with two magnetically coupled coils. A resonance circuit is used to raise the induced voltage and current of the secondary coil. Its resonance frequency depends on the internal resistance of circuit and the transferred energy. Because the transferred energy usually changes in wide range, the output voltage is unstable and the energy transferring efficiency decrease. A push-pull class E amplifier is usedto generate high frequency AC voltage. To maintain proper resonance frequency, the voltage output of the amplifier was continuously monitored and adjusted to the optimized resonance frequency. Because of its high frequency (370 kHz), a phase lockedloop circuit and a comparator are used to monitor the output waveform. The results of experimentaldata show that the PLL circuit can increase the transmission efficiency and stabilize the output voltage of TET.