• The Journal of Information Technology
• /
• v.3 no.1
• /
• pp.29-36
• /
• 2000

Viterbi decoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3 bit soft decision and traceback depth of ${\Gamma}=96$ for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.10C
• /
• pp.597-604
• /
• 2011

In this paper, we propose group Manchester code (GM) modulation scheme for medical in-body wireless body area network (WBAN) systems. In IEEE, the WBAN system is assigned as 802.15. Task Group 6 (TG 6), and the related standardization is being progressed, Recently, in this Group, group pulse position modulation (GPPM), which can obtain data rate increase by grouping pulse position modulation (PPM) symbols, is proposed as a new modulation scheme for low-power operation of WBAN system. However, the conventional method suffers from BER performance degradation due to the absence of gray coding and its demodulation characteristics. Therefore, in this paper, we propose a modified GM scheme which groups Manchester code instead of PPM. In the proposed GM scheme, a low-complexity maximum likelihood (ML) demodulation method is employed in order to maximize the BER performances, Also, log likelihood ratio (LLR) decision method is proposed to employ the Turbo code as forward error correction (FEC), Finally, we verified that the proposed method has a good performance and is an appropriate scheme for in-body WBAN system through extensive performance evaluation.

• Aerospace Engineering and Technology
• /
• v.8 no.1
• /
• pp.179-186
• /
• 2009

This paper describes the design and implementation for spread spectrum FTS encoder and decoder. The FTS command format is defined by 64 bit encrypted packet that contains all required information relayed between the ground and the vehicle. Encryption is accomplished using the Tripple-DES encryption algorithm in block encryption form. The proposed FTS encoder and decoder is using the Convolution Encoding and Viterbi Decoding for forward error correction. The Spread Spectrum Modulation is done using a PN code, which is 256 bit gold code. The simulation result shows that the designed FTS decoder is compatible with the designed FTS encoder.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.1
• /
• pp.25-34
• /
• 2012

This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.4
• /
• pp.277-284
• /
• 2001

Viterbi algorithm is widely used in digital communication system for FEC(forward error correction). Each communication systems based on the Viterbi algorithm use specific Viterbi decoder which has different code parameter values. Even if Viterbi decoder has the same code parameters, it can be varied by the design architecture adopted. We propose the parameterized VHDL model generator for the efficiency of the design. It makes it possible to achieve shorter design time and lower design cost. The model generator searches the design space available and finds out the optimal design point to generate a decoder model.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.04a
• /
• pp.681-684
• /
• 2011

최근 IEEE 802.11 WLAN(Wireless Local Area Network)에서 실시간 멀티미디어 서비스가 증가하고 있다. WLAN 의 패킷 전송방식은 Unicast 또는 Broadcast 방식이 있다. Unicast 방식은 재전송을 포함하여 유실율이 적으나 사용자가 증가할수록 AP 에서 필요한 무선 자원의 크기가 증가한다. 무선 자원의 크기가 증가하면 AP 부하가 증가하여 서비스 수용에 한계가 있다. Broadcast 방식은 사용자 수에 상관 없이 무선 자원의 크기가 일정하나, 패킷 유실율이 높다. 본 논문에서는 이러한 문제점을 해결하기 위해 Broadcast 와 FEC(Forward Error Correction) Erasure Code 기반 기술을 적용하는 것을 제안한다. 방송 패킷을 이용 AP 의 부하를 줄이고, Reed Solomon Erasure Code 를 적용하여 패킷 유실 복구율을 높인다. 이러한 방법을 통하여 다수의 사용자에게 안정적인 실시간 멀티미디어 방송 서비스를 제공 할 수 있다. 제안한 방법을 검증하기 위해 Android Platform 에서 FEC 적용 유무에 따른 수신율을 측정하였다. 그 결과 유실율 30%미만인 Broadcast 환경에서 96.4% 이상의 수신율을 보였다.

• ETRI Journal
• /
• v.27 no.5
• /
• pp.525-532
• /
• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.10
• /
• pp.72-79
• /
• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• Journal of electromagnetic engineering and science
• /
• v.6 no.3
• /
• pp.147-154
• /
• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• Journal of the Institute of Convergence Signal Processing
• /
• v.3 no.4
• /
• pp.67-73
• /
• 2002

There have been increased concerns on mobile stratospheric communication system(SCS) for the purpose of advanced service of personal and high speed communication systems. In fact, this SCS is considered and studied for IMT-2000 service by ITU. Although, it is important to make accurate channel model for prediction of the SCS performance, there is no measured channel data in this system. Thus, in this paper, we estimate the performance of SCS bye use of channel model provided by Corazza(2) and modified by You(3). And also, the effects of channel codings on system performance are analyzed by deriving bit error performance based on realistic Rician log-normal fading channel models. The performance results are divided into three kinds of areas with three kinds of elevation angles 20$^\cire$, 45$^\cire$, and 80$^\cire$. And also the effects of forward error correction channel codings on system performance with Hamming(7,4), HCH( IS,7) and convolutional code of constraint length 3 and code rate R=1/2.