Browse > Article

High-Performance Variable-Length Reed-Solomon Decoder Architecture for Gigabit WPAN Applications  

Choi, Chang-Seok (School of Information and Communication Engineering, Inha University)
Lee, Han-Ho (School of Information and Communication Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.1, 2012 , pp. 25-34 More about this Journal
Abstract
This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.
Keywords
Reed-Solomon code; forward error correction; decoder; variable-length; wireless personal area network;
Citations & Related Records
연도 인용수 순위
  • Reference
1 S. B. Wicker, "Error Control Systems for Digital Communication and Storage," Prentice Hall,1995.
2 D. V. Sarwate and N. R. Shanbhag, "High-speed Architecture for Reed-Solomon decoders" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 5, pp. 641-655, Oct. 2001.   DOI
3 H. Lee, "High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder," IEEE Trans. on VLSI Systems, vol. 11, no.2 pp. 288-294, April 2003.
4 H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen and I. S. Reed, "A VLSI Design of a Pipeline Reed-Solomon Decoder," IEEE Trans. on Computers, vol. C-34, no.5, pp. 393-403, May 1985.   DOI
5 S. Lee, H. Lee, J-Y. Shin, and J-S. Ko, "A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders," 2007 IEEE International Symposium on Circuits and Systems (ISCAS2007), pp. 901-904, May 2007.
6 S. Lee, C-S. Choi and H. Lee, "Two-parallel Reed-Solomon based FEC Architecture for Optical Communications," IEICE Electronics Express, vol. 5, no.10, pp.374-380, May 2008.   DOI
7 C-S. Choi and H. Lee, "High-Speed Low-Complexity Three-Parallel Reed-Solomon Decoder for 6-Gbps mmWAVE WPAN Systems," European Conference on Circuit theory and Design 2009 (ECCTD'09), pp. 515-518, Aug. 2009.
8 W. Liu, J. Rho, and W. Sung, "Low-power high-throughput BCH error correction VLSI design for multilevel cell NAND flash memories," in Proc. IEEE Workshop Signal Process. Syst. (SiPS): Des. Imple., pp. 248-253, Oct. 2006.
9 "Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for High Rate Wireless Personal Area Networks (WPANs): Amendment 2: Millimeter-wave based Alternative Physical layer Extension," IEEE P802.15.3c/D00. 2008.
10 "High Rate 60GHz PHY, MAC and HDMI PAL" Standard ECMA-387, 1st Edition, Dec.2008. vol. 37, no. 11, pp. 1565-1573, Nov. 2002.