• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• ETRI Journal
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• v.36 no.4
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• pp.635-642
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• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.18-24
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• 2007

As VLSI technology scales to nano-meter order, relatively increasing global wire-delay has added complexity to system design. Global wire-delay could be reduced by inserting pipeline-elements onto wire but it should be coupled with LIP(Latency Intensive Protocol) to have correct system timing. This combination however, drops the throughput although it ensures system functionality. In this paper, we propose a computation method useful for minimizing throughput deterioration when pipeline-elements are inserted to reduce global wire-delay. We apply this method while placing blocks in the floorplanning stage. When the necessary for this computation is reflected on the floorplanning cost function, the throughput increases by 16.97% on the average when compared with the floorplanning that uses the conventional heuristic throughput-evaluation-method.

• Journal of IKEEE
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• v.16 no.3
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• pp.197-202
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• 2012

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1021-1024
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• 1998

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.598-603
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• 2008

Sequence-Pair(SP)는 플로어플랜을 표현하는 모델 중 하나로써, 일반적으로 SP 모델을 사용하는 플로 어프래너 (floorplanner)는 Simulated-Annealing (SA) 알고리즙을 통해 해 탐색 과정을 수행한다. SP 모델을 이용한 다양한 논문에서 플로어플랜 성능 향상을 위해 평가함수의 개선과 스케줄링 기법 향상을 모색하였으며, 평가함수의 경우 O(nlogn) 시간 알고리즘이 존재한다. 본 논문에서는 SP 모델을 이용한 SA 기법에서 SA의 해 탐색 과정 중 초기 해 탐색 시점에서 좋은 해를 빠르게 찾을 수 있는 방법을 제안한다. 제안 기법은 기존의 SA 프레임펙을 수정한 2단계 SA 알고리즘으로써 SP에 대응하는 배치를 압축하고 압축한 배치를 역변환하는 과정으로 구성된다. 실험과 결과를 통해 제안기법의 효과를 보이며, 평균적으로 동일한 SA 환경 하에서 제안기법이 최종결과 면에서 우수함을 보인다.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.186-192
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• 2014

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.3
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• pp.217-230
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• 2009

In this paper we propose a new CBL-based floorplan method that accommodates pre-placed blocks. We identify the problem of the previous CBL-based pre-placed block floorplan method, and suggest the solution method of this problem. In our method, CBLs consisting of only free blocks are perturbed and maintained during the simulated annealing. Pre-placed blocks are inserted during packing in such a way that the topology of the CBL after insertion of a pre-placed block resembles the topology before insertion. Thus, even with the inclusion of pre-placed blocks, the searching effort via simulated annealing yields acceptable results. Experimental results show that our floorplan method places pre-placed blocks effectively and efficiently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.28-36
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• 2009

Sequence-Pair(SP) model represents the topological relation between modules. In general, SP model based floorplanners search solutions using Simulated-Annealing(SA) algorithm. Several SA based floorplanning techniques using SP model have been published. To improve the performance of those techniques they tried to improve the speed for evaluation function for SP model, to find better scheduling methods and perturb functions for SA. In this paper we propose a two phase SA based algorithm. In the first phase, white space between modules is reduced by applying compaction technique to the floorplan obtained by an SP. From the compacted floorplan, the corresponding SP is determined. Solution space has been searched by changing the SP in the SA framework. When solutions converge to some threshold value, the first phase of the SA based search stops. Then using the typical SA based algorithm, ie, without using the compaction technique, the second phase of our algorithm continues to find optimal solutions. Experimental results with MCNC benchmark circuits show that how the proposed technique affects to the procedure for SA based floorplainning algorithm and that the results obtained by our technique is better than those obtained by existing SA-based algorithms.