• Proceedings of the Korea Society for Industrial Systems Conference
• /
• 2002.11a
• /
• pp.363-370
• /
• 2002

A substrate network model characterizing substrate effect of submicron MOS transistors for RF operation and its parameter extraction with physically meaningful values are presented. The proposed substrate network model includes a single resistance and inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed with out any optimization. The proposed modeling technique has been applied to various-sized MOS transistors. Excellent agreement the measurement data and the simulation results using extracted substrate network model up to 30㎓

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.388-388
• /
• 2013

현대 사회에서 고집적 및 고성능의 전자소자의 필요성은 지속적으로 요구되고 있으며, 투명하거나 플렉서블한 특성의 필요성에 따라 이에 대한 기술개발이 이루어지고 있다. 특히, 이러한 특성을 만족하면서 대면적화 및 저온 공정의 특성을 지니는 유기물 반도체가 주목받고 있고, 이를 이용하여 OLED (Organic Light Emitting Diode), OTFT (Organic Thin Film Transistor)와 같은 다양한 유기물 반도체 소자가 개발되고 있다. 대표적인 예로는이 있다. 유기물 반도체 소자의 특성을 이용한 메모리 소자 또한 연구 및 개발이 지속되고 있으며, 유연성과 낮은 공정가격 등의 특성을 가지는 나노 입자들이 기존 Floating Gate의 대체물로 각광받고 있다. 본 논문에서는 MIS (Metal/Insulator/Semiconductor) 구조를 제작하고, Insulator 내부에Core/Shell 구조를 가지는 CdSe/ZnS 나노 입자를 부착하여 메모리 소자의 특성 확인 및 단위 면적당 개수에 따른 특성 변화를 확인하고자 하였다. 합성된 PVP (Poly 4-Vinyl Phenol)를 Insulator 층으로 사용하였으며 단위 면적당 나노 입자의 개수를 조절하여 제작된 MIS 소자를 Capacitance versus Voltage (C-V) 측정을 통하여 변화특성을 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2008.08a
• /
• pp.144-145
• /
• 2008

• ETRI Journal
• /
• v.33 no.3
• /
• pp.393-400
• /
• 2011

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 ${\mu}m$ CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 ${\mu}W$).

• Proceedings of the Korean Vacuum Society Conference
• /
• 2007.08a
• /
• pp.307-307
• /
• 2007

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.50 no.2
• /
• pp.87-92
• /
• 2001

This paper proposes a new content-addressable memory implemented with an analog array which has linear writing and erasing characteristics. The size of the array in this memory is $2{\times}2$, which is a reasonable structure for checking the disturbance of the unselected cells during programming. An intermediate voltage, Vmid, is used for preventing the interference during programming. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We simulate the function of the mechanism by means of Hspice with 1.2${\mu}m$ double poly CMOS parameters of MOSIS fabrication process.

• Journal of Power Electronics
• /
• v.16 no.1
• /
• pp.74-83
• /
• 2016

A new family of zero-voltage-transition converters with synchronous rectification is introduced in this study. Soft switching condition for all the converter operating points is provided in the proposed converters. The reverse recovery losses of the rectifier switch body diode are also eliminated. In comparison with the main switch voltage stress, the auxiliary switch voltage stress is reduced significantly. The auxiliary switch does not need the floating gate drive. The auxiliary inductor is coupled with the main converter inductor, and the leakage inductor is used as the resonance inductor. Thus, all inductors of the proposed converter can be implemented on a single core. The other features of the proposed converters include no extra voltage and current stresses on the main converter semiconductor elements. Theoretical analysis for a synchronous buck converter is presented in detail, and the validity of the theoretical analysis is justified with the experimental results of a prototype buck converter with 180 W and 80 V to 30 V.

• Transactions on Electrical and Electronic Materials
• /
• v.15 no.1
• /
• pp.37-40
• /
• 2014

A novel memory is reported, in which $Ge_2Sb_2Te_5$ (GST) has been used as a floating gate. The threshold voltage was shifted due to the phase transition of the GST layer, and the hysteretic behavior is opposite to that arising from charge trapping. Finite Element Modeling (FEM) was adapted, and a new simulation program was developed using c-interpreter, in order to analyze the small shift of threshold voltage. The results show that GST undergoes a partial phase transformation during the process of RESET or SET operation. A large $V_{TH}$ shift was observed when the thickness of the GST layer was scaled down from 50 nm to 25 nm. The novel 1 transistor PCM (1TPCM) can achieve a faster write time, maintaining a smaller cell size.

• Proceedings of the KIEE Conference
• /
• 1996.11a
• /
• pp.398-400
• /
• 1996

We present the implementation of the adaptive filter for EMG signal processing using VHDL. For making ASIC, the basic FPU(floating point processor), e.g., adder, multiplier and divider, are implemented with VHDL. The FPU is simulated and the controller for the RLSL(recursive least square lattice) algorithm of the adaptive filter is implemented. Then FPU and the controller are linked and simulated. Finally the models are synthesized and the gate level is implemented.

• Journal of the Korean Vacuum Society
• /
• v.22 no.3
• /
• pp.131-137
• /
• 2013

The thin insulator films for organic memory device were made by the plasma polymerization method using the styrene monomer which was not the wet process but the dry process. For the formation of stable plasma, we make an effort for controlling the monomer with bubbler and circulator system. The thickness of plasma polymerized styrene insulator layer was 430 nm, the thickness of the Au memory layer was 7 nm thickness of plasma polymerized styrene tunneling layer was 30, 60 nm, the thickness of pentacene active layer was 40 nm, the thickness of source and drain electrodes were 50 nm. The I-V characteristics of fabricated memory device got the hysteresis voltage of 45 V at 40/-40 V double sweep measuring conditions. If it compared with the results of previous paper which was the organic memory with the plasma polymerized MMA insulation thin film, this result was greater than 18 V, the improving ratio is 60%. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make the organic memory device with plasma polymerized styrene as the memory thin film.