• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.74-78
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• 2006

This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130nm HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1GHz operating speed.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.9-15
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• 2008

Microstructure and contact resistance of the Au-Sn solder joints were characterized after flip-chip bonding of the Au/Sn bumps processed by successive electrodeposition of Au and Sn. Microstructure of the Au-Sn solder joints, formed by flip-chip bonding at $285^{\circ}C$ for 30 sec, was composed of the $Au_5Sn$+AuSn lamellar structure. The interlamellar spacing of the $Au_5Sn$+AuSn structure increased by reflowing at $310^{\circ}C$ for 3 min after flip-chip bonding. While the Au-Sn solder joints formed by flip-chip bonding at $285^{\circ}C$ for 30 sec exhibited an average contact resistance of 15.6 $m{\Omega}$/bump, the Au-Sn solder joints reflowed at $310^{\circ}C$ for 3 min after flip-chip bonding possessed an average contact resistance of 15.0 $m{\Omega}$/bump.

• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.14-22
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• 2023

This paper presents a low-power flip-flop(FF) circuit that minimizes the transition of internal nodes by using a dual change-sensing method. The proposed dual change-sensing FF(DCSFF) shows the lowest dynamic power consumption among conventional FFs, when there is no input data transition. From the measured results with 65nm CMOS process, the power consumption has been reduced by 98% and 32%, when the data activity is 0% and 100%, respectively, compared to conventional transmission gate FF(TGFF). Further, compared to change-sensing FF(CSFF), the power consumption of proposed DCSFF is smaller by 30%.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.337-345
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• 2016

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

• Journal of the Optical Society of Korea
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• v.14 no.2
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• pp.137-141
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• 2010

We report, for the first time to our knowledge, observation of polarization bistability from 1.55-${\mu}m$ wavelength single-mode VCSELs of a conventional cylinder-shape under control of their driving current, and demonstration of all-optical flip-flop (AOFF) operations based on the bistability with optical set and reset pulse injection at a 50 MHz switching frequency. The injection pulse energy was less than 14 fJ. The average on-off contrast ratio of the flip-flopped signals was about 7 dB. These properties of the VCSELs will be potentially useful for future high-speed all-optical signal processing applications.

• Journal of the Korean Chemical Society
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• v.64 no.3
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• pp.145-152
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• 2020

Flip-flop rate constants were measured by dithionite assay of NBD-PE fluorescence in DMPC/POPC vesicles made of various DMPC/POPC ratios. The activation energy, enthalpy, entropy, and free energy were determined based on the transition state theory. We found that the activation energy, enthalpy, and entropy increased as the amount of POPC increased, but the activation free energy was almost constant. These experimental results and other similar studies allow us to propose that the POPC molecules included in DMPC vesicles affect the flip-flop motion of NBD-PE in DMPC/POPC vesicles via increasing the packing order of the ground state of the bilayer of the vesicles. The increase in the packing order in the ground state seems to be a result of the effect of the overall molecular shape of POPC with a monounsaturated tail group, rather than the effect of the longer tail group.

• Korean Journal of Materials Research
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• v.20 no.12
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• pp.681-685
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• 2010

The application of flip chip technology has been growing with the trend of miniaturization of electronic packages, especially in mobile electronics. Currently, several types of adhesive are used for flip chip bonding and these adhesives require some special properties; they must be solvent-free and fast curing and must ensure joint reliability against thermal fatigue and humidity. In this study, imidazole and its derivatives were added as curing catalysts to epoxy resin and their effects on the adhesive properties were investigated. Non-isothermal DSC analyses showed that the curing temperatures and the heat of reaction were dependent primarily on the type of catalyst. Isothermal dielectric analyses showed that the curing time was dependent on the amount of catalysts added as well as their type. The die shear strength increased with the increase of catalyst content while the Tg decreased. From this study, imidazole catalysts with low molecular weight are expected to be beneficial for snap curing and high adhesion strength for flip chip bonding applications.

• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.9
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• pp.916-921
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• 2009

The technology to inspect and measure an inner structure of micro parts has become an important tool in the semi-conductor industrial field with the development of automation and precision manufacturing. Especially, the inspection skill on the inside of highly integrated electronic device becomes a key role in detecting defects of a completely assembled product. X-ray inspection technology has been focused as a main method to inspect the inside structure. However, there has been insufficient research done on the customized inspection technology for the flip-chip assembly due to the interior connecting part of flip chip which connects the die and PCB electrically through balls positioned on the die. In this study, therefore, it is implemented to detect shape error of flip chip bonding without damaging chips using an x-ray inspection system. At this time, it is able to monitor the solder bump shape by introducing an edge-extracting algorithm (exponential approximation function) according to the attenuating characteristic and detect shape error compared with CAD data. Additionally, the bonding error of solder bumps is automatically detectable by acquiring numerical size information at the extracted solder bump edges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.