• 마이크로전자및패키징학회지
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• 제22권3호
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• pp.39-44
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• 2015

이방성 전도접착제를 이용하여 Cu/Au 칩 범프를 Cu 기판 배선에 플립칩 실장한 접속부에 대해 CNT-Ag 복합패드가 접속저항에 미치는 영향을 연구하였다. CNT-Ag 복합패드가 내재된 플립칩 접속부가 CNT-Ag 복합패드가 없는 접속부에 비해 더 낮은 접속저항을 나타내었다. 각기 25 MPa, 50 MPa 및 100 MPa의 본딩압력에서 CNT-Ag 복합패드가 내재된 접속부는 $164m{\Omega}$, $141m{\Omega}$ 및 $132m{\Omega}$의 평균 접속저항을 나타내었으며, CNT-Ag 복합패드를 형성하지 않은 접속부는 $200m{\Omega}$, $150m{\Omega}$ 및 $140m{\Omega}$의 평균 접속저항을 나타내었다.

• 마이크로전자및패키징학회지
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• 제10권4호
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• pp.81-86
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• 2003

상부 칩과 하부 기판이 모두 Si으로 구성되어 있는 플립칩 패키지 시편을 제조하여 Sn-3.5Ag 솔더범프의 electromigration 거동을 분석하였다. Sn-3.5Ag 솔더범프의 electromigration 테스트 초기부터 파단이 일어나기 직전까지는 플립칩 시편의 저항이 거의 변하지 않았으나, 파단이 발생하는 순간 저항값이 크게 증가하였다. 전류밀도 $3\times 10^4$∼$4\times 10^4$A/$\textrm{cm}^2$에서 Sn-3.5Ag 솔더범프의 electromigration에 대한 활성화 에너지는 ∼0.7 eV로 분석되었다. Sn-3.5Ag 솔더범프의 cathode 부위의 솔더/UBM 계면에서 void의 형성 및 전파에 의해 솔더범프의 파단이 발생하였다.

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.17-24
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• 2012

Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of $150^{\circ}C$ or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

• 마이크로전자및패키징학회지
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• 제25권4호
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• pp.155-161
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• 2018

강성도가 서로 다른 polydimethylsiloxane (PDMS) 탄성고분자와 flexible printed circuit board (FPCB)로 이루어진 PDMS/FPCB 구조의 강성도 국부변환 신축기판에 $100{\mu}m$ 직경의 Cu/Au 범프를 갖는 Si 칩을 anisotropic conductive adhesive (ACA)를 사용하여 플립칩 본딩 후, ACA내 전도성 입자에 따른 플립칩 접속저항을 비교하였다. Au 코팅된 폴리머 볼을 함유한 ACA를 사용하여 플립칩 본딩한 시편은 $43.2m{\Omega}$의 접속저항을 나타내었으며, SnBi 솔더입자를 함유한 ACA로 플립칩 본딩한 시편은 $36.2m{\Omega}$의 접속저항을 나타내었다. 반면에 Ni 입자를 함유한 ACA를 사용하여 플립칩 본딩한 시편에서는 전기적 open이 발생하였는데, 이는 ACA내 Ni 입자의 함유량이 부족하여 entrap된 Ni 입자가 하나도 없는 플립칩 접속부가 발생하였기 때문이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.39-45
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• 2000

A small camera module fabricated by including bare chip bonding methods is utilized to realize advanced mobile devices. One of the driving forces is the TOG (Tape On Glass) bonding method which reduces the packaging size of the image sensor clip. The TOG module is a new thinner and smaller image sensor module, using flip chip interconnection method with the ACP (Anisotropic Conductive Paste). The TOG production process was established by determining the optimum bonding conditions for both optical glass bonding and image sensor clip bonding lo the flexible PCB. The bonding conditions, including sufficient bonding margins, were studied. Another bonding method is the flip chip bonding method for DSP (Digital Signal Processor) chip. A new AC\ulcorner was developed to enable the short resin curing time of 10 sec. The bonding mechanism of the resin curing method was evaluated using FEM analysis. By using these flip chip bonding techniques, small camera module was realized.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.247-251
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• 2002

In this paper the maximum current carrying capability of ACAs flip chip joint is investigated based on two failure mechanisms: (1) degradation of the interface between gold stud bumps and aluminum pads; and (2) ACA swelling between chips and substrates under high current stress. For the determination of the maximum allowable current, bias stressing was applied to ACAs flip chip joint. The current level at which current carrying capability is saturated is defined as the maximum allowable current. The degradation mechanism under high current stress was studied by in-situ monitoring of gold stud bump-aluminum pad ACA contact resistance and also ACA junction temperature at various current level. The cumulative failure distributions were used to predict the lifetime of ACAs flip chip joint under high current stressing. These experimental results can be used to better understand and to improve the current carrying capability of ACA flip chip joint.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.763-768
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.