• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.9
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.270-277
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• 2003

Thermal performance of flip chip bonding with Sn-3.5Ag solder ball was studied. The temperature distribution was measured with IR(InfraRed) camera of 25 urn resolution. The measurement shows that most of the samples had much higher maximum temperature than average temperature. With central heater and 2.5 (W), the difference between maximum and average temperature is over $80^{\circ}C$. The distribution was influenced by the location of heater, the distance from heater to flip chip bonding, and the passivation opening of solder bumps. To reduce the maximum temperature, the bigger passivation opening, the smaller chip size, and the closer location of heater to flip chip bumps are preferrable.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.7-13
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• 2007

In the optical module for optical communications, the flip chip bonding is used fer the precise alignment of the optical fiber and optical device. In flip chip bonding, the optical device is aligned and welded while observing the alignment mark of substrate and chip by using flip chip bonder in order to bond the optical device at the exact position. In this research, optical passive alignment method of photodiode(PD) flip chip bonding is suggested for low cost optical subassembly. By using the visible He-Ne laser (633nm wavelength), photodiode is easily aligned with emitting spot on the optical fiber with the help of stereoscopic alignment system. We compensated wavelength dependent deviation about 4m to find out real alignment position of 1550nm input laser by ray tracing. The maximum optical coupling efficiency between the optical fiber and photodiode was about 23.3%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.4
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• pp.483-486
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• 2014

Although flip-chip interconnects have smaller parasitics than bonding wires, they should be carefully designed at 60 GHz. Insertion loss at a flip-chip transition may differ as much as 2 dB depending on design parameters. In this paper we present a comprehensive sensitivity analysis to optimize the flip-chip transition.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.138-140
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• 2001

Fluxless flip chip bonding using plasma & ultrasonic wave was investigated in order to evaluate the effect of plasma & ultrasonic treatment on the bondability of the Sn-3.5wt%Ag solder bumped die to TSM-coated glass substrate. The $Ar+10%H_2plasma$ was effective in removing tin oxide on solder surface. The die shear strength of the plasma-treated Si-chip is higher than that of non-treated specimen but lower than that of specimen bonded with flux. The die shear strength with the bonding load at 25W ultrasonic power increased to 0.8N/bump for all bonding temperature but decreased above 1.0N/bump.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.749-750
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• 2011

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2008.11a
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• pp.364-367
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• 2008

Finite element model and the basic experimental method have been developed to help the design of the transverse ultrasonic horn for flip-chip bonding. With two types of design the horn performance and ultrasonic characteristics are verified by using laser vibrometer. These analysis and experiment results can be the fundamental data for ultrasonic horn design considering the vibration modes and performance.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.10a
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• pp.645-646
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• 2006

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.27-31
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• 2003

RF characteristics of CPW(coplanar waveguide) pattern with bonding pads used in flip-chip packaging of GaAs is studied in the frequency range of 1 GHz to 35 GHz. Simulation, fabrication and evaluation are performed for the proposed patterns. Measurement results show proposed patterns have similar properties of $S_{11}$below -31 dB and $S_{21}$ above -0.19 dB with typical CPW In addition RF properties are improved with the increase of width of ground line. This indicates CPW structure with bonding pads keeps RF characteristics of typical CPW.