• Title/Summary/Keyword: Flexible microelectronics system

Search Result 11, Processing Time 0.023 seconds

Control of Position of Neutral Line in Flexible Microelectronic System Under Bending Stress (굽힘응력을 받는 유연전자소자에서 중립축 위치의 제어)

  • Seo, Seung-Ho;Lee, Jae-Hak;Song, Jun-Yeob;Lee, Won-Jun
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.23 no.2
    • /
    • pp.79-84
    • /
    • 2016
  • A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

Technical Trends of Stretchable Electrodes (신축성 전극 기술 개발 동향)

  • Choi, Su Bin;Lee, Cheul-Ro;Jung, Seung-Boo;Kim, Jong-Woong
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.26 no.3
    • /
    • pp.23-36
    • /
    • 2019
  • Stretchable electronic systems have recently been gaining more and more attention because of their potential applications in various implements such as electronic skins and wearable/shape-deformable electronics. An essential factor of the stable stretchable device implementation is that all the elements constituting the system must have sufficient elasticity and exhibit stable performances even under repetitive stretching conditions. In this paper, we review the latest research results to secure the stable stretchability of electrodes among the various components of the system.

Hybrid Multi-System-on-Chip Architecture as a Rapid Development Approach for a High-Flexibility System

  • Putra, Rachmad Vidya Wicaksana;Adiono, Trio
    • IEIE Transactions on Smart Processing and Computing
    • /
    • v.5 no.1
    • /
    • pp.55-62
    • /
    • 2016
  • In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.22 no.2
    • /
    • pp.11-19
    • /
    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Development of Transfer Method for Transparent Thin Film Transistor of Heat-treated Zinc Oxide Thin Film by Solution Process (용액공정을 이용한 열처리된 산화아연 박막의 투명한 박막 트랜지스터 구현을 위한 전사방법 개발)

  • Kwon, Soon Yeol;Jung, Dong Geon;Choi, Young Chan;Lee, Jae Yong;Kong, Seong Ho
    • Journal of the Semiconductor & Display Technology
    • /
    • v.17 no.2
    • /
    • pp.57-60
    • /
    • 2018
  • Recently, Thin-film transistors (TFTs) are fundamental building blocks for state-of-the-art microelectronics, such as flat-panel displays and system-on-glass. Zinc oxide thin films have the advantage that they can grow at low temperature and can obtain high charge movility. Also the zinc oxide thin film can be used to control the resistance according to the oxygen content, so it is very easy to obtain the desired physical properties. In this paper, we fabricated a zinc oxide thin film on a polished copper substrate through a solution process, then improved the crystallinity through a geat treatment porcess, and studied to transfer it on a flexible substrate after the heat treatment was completed.

Micro-LED Mass Transfer using a Vacuum Chuck (진공 척을 이용한 마이크로 LED 대량 전사 공정 개발)

  • Kim, Injoo;Kim, Yonghwa;Cho, Younghak;Kim, Sungdong
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.29 no.2
    • /
    • pp.121-127
    • /
    • 2022
  • Micro-LED is a light-emitting diode smaller than 100 ㎛ in size. It attracts much attention due to its superior performance, such as resolution, brightness, etc., and is considered for various applications like flexible display and VR/AR. Micro-LED display requires a mass transfer process to move micro-LED chips from a LED wafer to a target substrate. In this study, we proposed a vacuum chuck method as a mass transfer technique. The vacuum chuck was fabricated with MEMS technology and PDMS micro-mold process. The spin-coating approach using a dam structure successfully controlled the PDMS mold's thickness. The vacuum test using solder balls instead of micro-LED confirmed the vacuum chuck method as a mass transfer technique.

Manufacturing of Metal Micro-wire Interconnection on Submillimeter Diameter Catheter (서브-밀리미터 직경의 카테터 표면 위 금속 마이크로 와이어 접착 공정)

  • Jo, Woosung;Seo, Jeongmin;Kim, Taek-Soo
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.24 no.2
    • /
    • pp.29-35
    • /
    • 2017
  • In this paper, we investigated a manufacturing process of metal micro-wire interconnection on submillimeter diameter catheter. Over the years, flexible electronic researches have focused on flexible plane polymer substrate and micro electrode manufacturing on its surface. However, a curved polymer substrate, such as catheter, is very important for medical application. Among many catheters, importance of submillimeter diameter steerable catheter is increasing to resolve the several limitations of neurosurgery. Steering actuators have been researched for realizing the steerable catheter, but there is no research about practical wiring for driving these actuators. Therefore we developed a new manufacturing process for metal micro-wire interconnection on submillimeter diameter catheter. We designed custom jigs for alignment of the metal micro-wires on the submillimeter diameter catheter. An UV curing system and commercial products were used to reduce the manufacturing time and cost; Au micro-wire, UV curable epoxy, UV lamp, and submillimeter diameter catheter. The assembled catheter was characterized by using an optical microscope, a resistance meter, and a universal testing machine.

Trends of Researches and Technologies of Electronic Packaging Using Graphene (그래핀을 이용한 전자패키징 기술 연구 동향)

  • Ko, Yong-Ho;Choi, Kyeonggon;Kim, Sang Woo;Yu, Dong-Yurl;Bang, Junghwan;Kim, Taek-Soo
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.23 no.2
    • /
    • pp.1-10
    • /
    • 2016
  • This paper reports the trends of researches and technologies of electronic packaging using graphene. Electronic packaging is to provide the signal and electrical current among electronic components, to remove the heat in electronic systems or components, to protect and support the electronic components from external environment. As the required functions and performances of electronic systems or components increase, the electronic packaging has been intensively attracted attention. Therefore, technologies such as miniaturization, high density, Pb-free material, high reliability, heat dissipation and so on, are required in electronic packaging. Recently, graphene, which is a single two-dimensional layer of carbon atoms, has been extensively investigated because of its superior mechanical, electrical and thermal properties. Until now, many studies have been reported the applications using graphene such as flexible display, electrode, super capacitor, composite materials and so on. In this paper, we will introduce and discuss various studies on recent technologies of electronic packaging using graphene for solving the required issues.

Mechanical and Electrical Reliability of Silver Nanowire Film on Flexible Substrate (유연기판 위에 제작된 Silver Nanowire 필름의 기계 및 전기적 신뢰성 연구)

  • Lee, Yo Seb;Lee, Won Jae;Park, Jin Yeong;Choa, Sung-Hoon
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.23 no.4
    • /
    • pp.93-99
    • /
    • 2016
  • In this paper, we investigated the mechanical and electrical reliability of silver nanowire (AgNW) films. In particular, the durability and reliability of AgNW films were studied when the AgNW film was subjected to the bending deformation under current flow. The electrical durability of AgNW was evaluated by observing changes in heat generation and current density occurring in AgNW through voltage and current tests. The AgNW film showed a constant resistance change up to a bending radius of 2 mm and 200,000 cycles in the bending fatigue tests. The over-coating layer has an effect of improving the durability of the AgNW film. In the case of AgNW with the over-coating layer, heat was uniformly dissipated on the surface of AgNW film, whereas in the case of AgNW film without the over-coating layer, heat was generated locally. In the bending test under the current flow, the current density of the AgNW film was continuously decreased up to 52.4%. During bending, the AgNW was deformed due to mechanical deformation such as tensile, bending and sliding of the AgNW, consequently contact resistance of the AgNW was increased, leading to a electrical breakdown of AgNW by Joule heating. It was found that the application of the over-coating layer can improve the electrical and mechanical reliability of the AgNW film.

Effects of Encapsulation Layer on Center Crack and Fracture of Thin Silicon Chip using Numerical Analysis (봉지막이 박형 실리콘 칩의 파괴에 미치는 영향에 대한 수치해석 연구)

  • Choa, Sung-Hoon;Jang, Young-Moon;Lee, Haeng-Soo
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.25 no.1
    • /
    • pp.1-10
    • /
    • 2018
  • Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.