• Journal of rehabilitation welfare engineering & assistive technology
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• v.9 no.3
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• pp.195-201
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• 2015

In this study, IT education contents have been developed based on the u-Learning approach for people with hearing impairment, focusing on allowing the user to learn from anywhere and anytime. Specifically, this study applies HTML5 to implementing IT education contents(JSP, Oracle) for the deaf because HTML5 enables the learner to access the contents through both web and mobile device on various platforms including android, Mac OS, and PC etc. The results of this study are as follows: First, the online computer courses are mostly supposed to be compatible with diverse types of mobile devices. However, some of the contents could not be run on applications residing in web and mobile devices because the contents tend to be developed using FLASH. HTML5 is the effective way to overcome the compatibility problem. Second, FLASH and HTML5 contents authoring tools have been compared in terms of their strong and weak points by applying the developed contents to those tools. The study also suggests that the future work would be needed in order to implement wide variety of event functions with HTML5. Lastly, design strategies enabling access through web and mobile devices have been analyzed in accordance with u-Learning design guidelines for the deaf and mobile application accessibility guidelines. However, in the latter case, the future work regarding design guidelines needs to be conducted to improve the educational accessibility depending on the level of impairment.

• Bulletin of the Korean Space Science Society
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• 2009.04a
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• pp.64.3-64.3
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• 2009

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Proceedings of the Korea Water Resources Association Conference
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• 2017.05a
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• pp.21-21
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• 2017

최근 서울, 부산, 울산 등에서 도시 돌발홍수가 빈번히 발생하고 있고 이에 따른 인명 손실 및 재산 피해가 빠르게 증가하고 있다. 그러나 집중 호우의 대부분은 저고도 대기에서 생성 및 발달되며, 소멸까지의 시간은 2-3 시간에 불과하여 기존의 우리나라 수문기상 관측시스템은 이러한 유형의 강우량 예측에 많은 어려움을 겪고 있는 실정이다. 이 문제를 해결하기 위해 기상, 재난 관련 정부 기관들이 저고도 수문기상 관측을 위한 도시형 X-밴드 레이더 네트워크 구축을 계획하고 있다. 본 연구의 목적은 그보다 선행하여 돌발성 수문기상 재해연구를 위해 한국건설기술연구원에서 도입한 X-band 이중 편파 레이더 시스템을 이용하여 보다 간단하고 정확한 재난 감시 및 예경보 시스템을 개발하는데 있다. 본 연구에서는 X-밴드 레이더 데이터로부터 추정된 정량적 강수량을 모니터링 하여 도시 지역의 돌발홍수를 자동으로 경고하는 방법을 제안한다. 또한 Google 어스 플랫폼을 사용하여 정확한 3D QPE-GIS 매칭 기법을 개발함으로써, 심각한 수문기상 현상이 발생하는 정확한 위치를 추적하고 직관적인 경보서비스를 가능케 한다. 본 연구에서 제안하는 경보시스템은 레이더 데이터 분석도구, 위험결정 도구 및 위험경고 표시 도구의 세 가지 기술로 구성된다. 제안된 돌발홍수 경보시스템은, 시뮬레이션을 통해 X-밴드 레이더 데이터로부터 정량적 강수량이 계산되며, GIS 상에서 레이더 반사도 및 강우강도가 3차원 이미지 형태로 표시된다. 그런 다음 Google 어스에서 3D 큐브 블록으로 대표되는 강수량이 동시에 누적표출 되도록 설계되었다. 또한 분석된 X-밴드 레이더 데이터로부터 지역별 누적 강수량을 업데이트 및 모니터링하고 기 설정된 돌발홍수 발생 한계치(trigger)에 도달하면 홍수경보 메시지를 표시한다. 향후, 제안된 경보시스템에 대한 기술적 도구를 개선하면서 대규모 수문기상 레이더 네트워크로 광범위한 강우를 모니터링하면 전국적인 돌발홍수 경보시스템으로 확대가 가능하다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.339.1-339.1
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• 2014

In this paper we studied the application of inter-poly dielectric as silicon dioxide-like film was deposited by the higher energy assisting deposition (HEAD) process the modified CCP process, which enables low temperature (LT) process and improving film density. In these experiments the relative hydrogen concentration of $SiO_2$-like films deposited on silicon substrate were analyzed by the secondary ion mass spectroscopy (SIMS) and it was shown that our lower hydrogenated oxide (LHO) film prepared by HEAD process with the precursor contained the siloxane species had lower hydrogen concentration, $8{\times}10{\cdot}^{22}cm{\cdot}^3$ than that of the commercial undoped silicon glass (USG) film ($1{\times}10{\cdot}^{21}cm{\cdot}^3$) prepared by the high density plasma-chemical vapor deposition (HDP-CVD). We consider that the LHO film deposited by HEAD process used as high performance material into Flash memory devices.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.46-46
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• 2018

메모리 소자의 수요가 데스크톱 컴퓨터의 정체와 모바일 기기의 폭발적인 증가로 NAND flash 메모리의 고집적화로 이어져서 3차원 집적 기술의 고도화가 중요한 요소가 되고 있다. 1 mm 정도의 얇은 웨이퍼 상에 만들어지는 메모리 소자는 실제 두께는 몇 마이크로미터 되지 않는다. 수직방향으로 여러 장의 웨이퍼를 연결하면 폭 방향으로 이미 거의 한계에 도달해있는 크기 축소(shrinking) 기술에 의지 하지 않고서도 메모리 소자의 용량을 증대 시킬 수 있다. CPU, AP등의 논리 연산 소자의 경우에는 발열 문제로 3D stacking 기술의 구현이 쉽지 않지만 메모리 소자의 경우에는 저 전력화를 통해서 실용화가 시작되었다. 스마트폰, 휴대용 보조 저장 매체(USB memory, SSD)등에 수 십 GB의 용량이 보편적인 현재, FEOL, BEOL 기술을 모두 가지고 있는 국내의 반도체 소자 업체들은 자연스럽게 TSV 기술과 이에 필요한 장비의 개발에 관심을 가지게 되었다. 특히 이 중 TSV용 스퍼터링 장치는 transistor의 main contact 공정에 전 세계 시장의 90% 이상을 점유하고 있는 글로벌 업체의 경우에도 완전히 만족스러운 장비를 공급하지는 못하고 있는 상태여서 연구 개발의 적절한 시기이다. 기본 개념은 일반적인 마그네트론 스퍼터링이 중성 입자를 타겟 표면에서 발생시키는데 이를 다시 추가적인 전력 공급으로 전자 - 중성 충돌로 인한 이온화 과정을 추가하고 여기서 발생된 타겟 이온들을 웨이퍼의 표면에 최대한 수직 방향으로 입사시키려는 노력이 핵심이다. 본 발표에서는 고전력 이온화 스퍼터링 시스템의 자기장 해석, 냉각 효율 해석, 멀티 모듈 회전 자석 음극에 대한 동역학적 분석 결과를 발표한다. 그림1에는 이중 회전 모듈에 대한 다물체 동역학 해석을 Adams s/w package로 해석하기 위하여 작성한 모델이고 그림2는 180도 회전한 서브 모듈의 위상이 음극 냉각에 미치는 효과를 CFD-ACE+로 유동 해석한 결과를 나타내고 있다.

• Journal of the Korean Institute of Gas
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• v.23 no.6
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• pp.39-60
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• 2019

Korea Gas Safety Corporation is developing consequence analysis system for combustible materials release events to enhance risk assessment technology and its efficiency. Unlike general consequence analysis programs, the final consequence area was implemented through ETA analysis based on API-581 standard, and a convenient user interface was constructed based on HTML5-based responsive web technology. In addition, a phase equilibrium module using third-order state equations (such as Peng-Robinson, SRK, and RK) and fugecity was implemented to analyze the mixture quality. Also. using the consequence analysis algorithm introduced in CCPS books and TNO Yellow Book, we developed material leak analysis module, fireball, pool fire, jet fire, flash fire, and vapor cloud explosion consequence assessment module. In addition, the conditions for calculating the safety distance were prepared with using the control values in the EIGA standard, PAC, and Bevi Reference Book.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.30 no.5
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• pp.174-182
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• 2020

The printed electronics field using ink-jet printing technology is in the spotlight as a next-generation technology, especially ink-jet 3D printing, which can simultaneously discharge and precisely control various ink materials, has been actively researched in recent years. In this study, complex structure of an insulating layer and a conductive layer was fabricated with photo-curable silica ink and PVP-added Cu nano ink using ink-jet 3D printing technology. A precise photocured silica insulating layer was designed by optimizing the printing conditions and the rheological properties of the ink, and the resistance of the insulating layer was 2.43 × 10¹³ Ω·cm. On the photo-cured silica insulating layer, a Cu conductive layer was printed by controlling droplet distance. The sintering of the PVP-added nano Cu ink was performed using an IPL flash sintering process, and electrical and mechanical properties were confirmed according to the annealing temperature and applied voltage. Finally, it was confirmed that the resistance of the PVP-added Cu conductive layer was very low as 29 μΩ·cm under 100℃ annealing temperature and 700 V of IPL applied voltage, and the adhesion to the photo-cured silica insulating layer was very good.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).