• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.298-305
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• 2004

This paper presents an error compensation method for a fixed-width modified Booth multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50％ by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 40％ reduction in area and power consumption of a multiplier compared with the ideal multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.33-38
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• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.29-34
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• 2005

The maximum quantization error has serious effect on the performance of fixed-width multipliers that receive W-bit inputs and produce W-bit products. In this paper, we analyze the error bound of fixed-width modified Booth multipliers. Then, the estimation method for the number of additional columns for fixed-width multipliers is proposed to limit the maximum quantization error within a desired bound. In addition, it is shown that our methodology can be extended to reduced-width multipliers. By simulations, it is shown that the proposed error analysis method is useful to the practical design of fixed-width modified Booth multipliers.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.199-205
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• 2011

This paper presents a QR decomposition processor by exploiting Givens rotation for the GDFE (Generalized Decision Feedback Equalizer). A Givens rotation consists of phase extraction, sine/cosine generation and angle rotation parts. Combining two-stage method (coarse and fine stage) and the fixed-width modified-Booth multiplier, we design an efficient QR decomposition processor. By simulations, it is shown that the proposed QR decomposition processor can be a feasible solution for GDFE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.8C
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• pp.832-837
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• 2005

This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, modified Booth encoder signals (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups (major/minor group) depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that the performance of the proposed method is close to that of the rounding method and much better than that of the truncation method and conventional method. It is also shown that the proposed method leads to up to $28\%\;and\;27\%$ reduction in area and power consumption compared with the ideal squarers, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.25 no.9
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• pp.1219-1226
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• 2001

Pressure drops were measured for the flow boiling process within horizontal rectangular channels. The gap between the upper and the lower plates of each channel ranges from 0.4 to 2mm while the channel width being fixed to 20mm. Refrigerant 113 was used as the test fluid. The mass flux ranges from 50 to 200kg/㎡s and the channel walls were uniformly heated up to 15kW/㎡. The quality range covers from 0.15 to 0.75. The present experimental conditions coincide with the operating conditions of compact heat exchangers in which the liquid and gas flows are laminar and turbulent. The measured results were well represented by the two-phase frictional multiplier of Lee (2001) which has been developed for air-water two-phase flows within the deviation of $\pm$20%.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.861-864
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• 2001

많은 멀티미디어와 DSP 응용에서 입력과 출력 데이터 길이가 같은 고정 길이 곱셈기가 요구된다. 고정 길이 곱셈기는 확률적인 추정에 근거한 적절한 보상 바이어스를 더해줌으로써 일반적인 병렬 곱셈기와 비교하여 50%의 면적을 줄일 수 있다. 본 논문에서는 CSD 곱셈기에 적합한 고정길이 곱셈기의 구조를 제시하고 전파 캐리 선택절차를 이용한 부호확장제거방법과 결합함으로서 새로운 곱셈기구현 방안을 제시한다. 이 곱셈기의 응용으로서 SSB/BPSK-DS/CDMA 전송방식에 사용되는 힐버트 트랜스포머를 43탭 FIR 필터로 구현하고 기존의 compensation 벡터 방법과 비교하여 약 34%의 부호확장 오버헤드를 줄일 수 있음을 보인다.

• Textile Coloration and Finishing
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• v.13 no.6
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• pp.428-434
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• 2001

This study surveys the fiber behavior in yam formation and the Physical properties of Solo-spun yarn. The specimens were made by six types of Solo-spun rollers with fixed twist multiplier In the previous part, the physical properties such as yarn count, evenness, strength, and breaking elongation of these yams were compared with the properties of ring shun yarns and analysed with the mechanism of Solo-spun yarn formation. In the second part of this report, the abrasion resistance and hairiness were discussed wish respect to the micro yarn structures. The narrower the groove width of Solo-spun roller is, the more active the bulk fibers migration is. The Solo-spun film structure has two groups. One is shorter than the others one in longitudinal direction of yarn and has the same structure as ring-spun yarn, which is derided from the smooth zone on the surface of Solo-spun roller. The other one is longer than the former and there are the wrapping fibers. This part is derived from the conflicted grooves on the surface of Solo-spun troller.

• Textile Coloration and Finishing
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• v.13 no.6
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• pp.70-70
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• 2001

This study surveys the fiber behavior in yarn formation and the Physical properties of Solo-spun yarn. The specimens were made by six types of Solo-spun rollers with fixed twist multiplier In the previous part, the physical properties such as yarn count, evenness, strength, and breaking elongation of these yarns were compared with the properties of ring spun yarns and analysed with the mechanism of Solo-spun yarn formation. In the second part of this report, the abrasion resistance and hairiness were discussed with respect to the micro yarn structures. The narrower the groove width of Solo-spun roller is, the more active the bulk fiber migration is. The Solo-spun yarn structure has two groups. One is shorter than the other one in longitudinal direction of yarn and has the same structure as ring-spun yarn, which is derived from the smooth zone on the surface of Solo-spun roller. The other one is longer than the former and there are the wrapping fibers. This part is derived from the conflicted grooves on the surface of Solo-spun roller.