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Design of Low Error Fixed-Width Group CSD Multiplier  

Kim, Yong-Eun (Div. of Electronic & Information Engineering Chunbuk National University)
Cho, Kyung-Ju (Korea Association of Aids to Navigation)
Chung, Jin-Gyun (Div. of Electronic & Information Engineering Chunbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.9, 2009 , pp. 33-38 More about this Journal
Abstract
The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.
Keywords
그룹 CSD 곱셈기;modified Booth 곱셈기;양자화 오차;고정길이 곱셈기;
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