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Fixed-Width Booth-folding Squarer Design  

Cho Kyung-Ju (전북대학교 전자정보공학부 정보통신학과)
Chung Jin-Gyun (전북대학교 전자정보공학부 정보통신학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.30, no.8C, 2005 , pp. 832-837 More about this Journal
Abstract
This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, modified Booth encoder signals (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups (major/minor group) depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that the performance of the proposed method is close to that of the rounding method and much better than that of the truncation method and conventional method. It is also shown that the proposed method leads to up to $28\%\;and\;27\%$ reduction in area and power consumption compared with the ideal squarers, respectively.
Keywords
Squarer; fixed-width; Booth-folding; quantization error;
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