• E2M - 전기 전자와 첨단 소재
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• 제9권4호
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• pp.336-343
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• 1996

We have studied the preparation and the properties of $Ba_{1-x}$Sr$_{x}$TiO$_{3}$(BST) thin films by using the sol-gel method. Through the comparison of the effects of various solvents and additives in making solutions, we establish the production method of the stable solution which generates the high quality of BST film. We also set up the heat-treatment conditions for depositing the BST thin film through the TGA and XRD analyses. Through the comparison of the surface conditions of BST films deposited on Pt/Ta/SiO$_{2}$/Si and Pt/Ti/SiO$_{2}$/Si substrates, we find that Ta is more efficient diffusion barrier of Si than Ti so that Ta layer prevents the formation of hillocks. We fabricate the planar type capacitor and measure the dielectric properties of the BST thin film deposited on the Pt/Ta/SiO$_{2}$/Si substrate. Dielectric constant and dielectric loss tangent at 1V, 10kHz, and leakage current density at 3V of the BST thin film are 339, 0.052 and 13.3.mu.A/cm$^{2}$, respectively.ely.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.342-345
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• 2002

As the size of chip components and module decreases, new patteming method for fine line and geometry is needed. So far, in LTCC(Low Temperature Cofired Ceramic) process, screen printing method has been used generally. But screen printing method has some disadvantages as follows. First, the geometry including line, vias, etc. smaller than $100{\mu}m$ can't be evaluated easily. Second, the patterned dimension is different from designed value, which makes distortion in charactersitics of not only chip components but also modules. Thick film lithography has advantages of thick film screen printing process, low cost and thin film process, fine line feasibility. Using this method, the line with $30{\mu}m$ width and the geometry with expected dimension can be evaluated. In this study, the fine line with $35{\mu}m$ line/space is formed and the embedded capacitor with very small tolerance is developed using thick film lithography.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.412-415
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• 2003

[ $Si_3N_4$ ] thin film is the good material to fabricate the capacitors at MMIC processes. Normally, $Si_3N_4$ thin films is used to dielectric in the MIM capacitor and film thickness is $2000\;{\AA}$. Insulator(or dielectric) was deposited by PECVD at our MIM structure with air bridge which connect between top metal and contact pad. We optimized PECVD process to fabricate the good capacitors which can be applied at the true MMIC. The thickness of our $Si_3N_4$ thin films was $1000\;{\AA}$ shallower than $2000\;{\AA}$, and their breakdown voltages were above 70V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.675-678
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• 2000

Using the principle of the cross capacitor, a precise system for measuring the electric constants of liquids has been developed. The four electrodes of the cross capacitor were formed around fused-silica tube by plating a gold film. The effect of a non-uniform tube wall ok the measured permittivity was investigated As the individual characteristics of the tubes were determined to be constant, the pure dielectric constants extracted from any effect of the fused-silica material could be precisely derived with uncertainty of less than ${\pm}$ 0.02∼0.05 %.

• 한국재료학회지
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• 제9권5호
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• pp.509-514
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• 1999

Interest in the integrated capacitors, which make it possible to reduce the size of and to obtain improved electrical performance of an electronic system, is expanding. In this study, $Ta_2$O\ulcorner thin film capacitors for MCM integrated capacitors were fabricated on a Upilex-S polymer film by DC magnetron reactive sputtering and the effects of low temperature annealing at various atmospheres and substrate surface morphology on the capacitor characteristics were discussed. The low temperature($150^{\circ}C$) annealing produced improved capacitor yield irrespective of the annealing at mosphere. But the leakage current of the $O_2$-annealed film was larger than that of any other films. This is presumably mosphere. But the leakage current of the $O_2$-annealed film was larger than that of any other films. This is presumably due to the change of the $Ta_2$O\ulcorner film surface by oxygen, which was explained by conduction mechanism study. Leakage current and breakdown field strength of the capacitors fabricated on the Upilex-S film were 7.27$\times$10\ulcornerA/$\textrm{cm}^2$ and 1.0 MV/cm respectively. These capacitor characteristics were inferior to those of the capacitors fabricated on the Si substrate but enough to be used for decoupling capacitors in multilayer package. Roughness Analysis of each layer by AFM demonstrated that the properties of the capacitors fabricated on the polymer film were affected by the surface morphology of the substrate. This substrate effect could be classified into two factors. One is the surface morphology of the polymer film and the other is the surface morphology of the metal bottom electrode determined by the deposition process. Therefore, the control of the two factors is important to obtain improved electrical of capacitors deposited on a polymer film.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.566-569
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• 2001

In this paper, we investigated the electrical characteristics through DC power at manufacturing the MIS capacitor insulator AIN thin film based on reactive sputtering method. In case of deposition temperature 250$^{\circ}C$, pressure 5mTorr, total flow rate 8sccm(Ar:4sccm N2:4sccm), AIN thin film was deposited with changing DC power. As DC power increses, resistivity is observed a little increase. When AIN thin film is deposited at 100W, the result shows leakage current 10$\^$-8/A/$\textrm{cm}^2$ at 0.1MV/cm. Otherwise, In case of depositing at 150W and 200W, the result shows that the characteristic of leakage current is under 10$\^$-9//$\textrm{cm}^2$ at 0.1MV/cm. In C-V characteristic with DC power, deep depletion phenomenon is observed at inversion region in 100W and 150W. In 200W, that phenomenon, however, was showed to decrease. It shows that the hysterisis increases with being increasing DC power.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.760-763
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• 2003

Low Temperature Cofired Ceramics (LTCC) technology is a promising technology to integrate many devices in a module by embedding passive components. For the module substrate, most LTCC structures have dielectric constants below 10 to reduce signal delay time. Some components, which need high dielectric constants, have not been yet embedded in LTCC module. So, embedding capacitor with high capacitance by applying another dielectrics with high dielectric constants in LTCC is an important issue to maximize circuit density in LTCC module. In this study, electrical properties of embedded capacitor fabricated by dielectric paste of high dielectric constants (K-100) and co-firing behavior with LTCC were investigated. To prevent camber development of co-fired structure, constrained sintering process was tested. Dielectric properties of embedded capacitors were calculated from their capacitance and impedance value. Temperature coefficient of capacitance were also measured.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.437-438
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• 2007

In this paper a embedded decoupling capacitor design with gap structure will be discussed. A novel structure is modeling and analization by High Frequency Structure Simulator (HFSS). Proposed capacitor have $2m{\times}2m$ in rectangular shape. The film thickness of copper/dielectric film/substrate is respectively 35um/20um/35um. A dielectric layer of BaTiO3/epoxy has the relative permittivity of 25. Compare of the planar decoupling capacitor, capacitance densities of this structure in the range of $55{\mu}F$/mm2 have been obtained with 50um gap while capacitance densities of planar structure $55{\mu}F$/mm2 in the same size. The frequency dependent behavior of capacitors is numerically extracted over a wide frequency bandwidth 500MHz-7GHz. The decoupling capacitor can work at high frequency band increasing the gap size.

• 전력전자학회지
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• 제9권5호
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• pp.21-24
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• 2004

• 전자공학회논문지D
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• 제36D권6호
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• pp.44-51
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• 1999

High density DRAM의 cell capacitor로 촉망 받고 있는 고유전체 BST박막 커패시터의 저 전계(<0.2MV/cm) 영역에서의 전기전도 현상을 분석하였다. 저 전계 영역에서 Pt/BST/Pt구조의 MIM 커패시터에 일정 전계를 인가한 후 전류를 측정하는 I(t)방법을 이용하여 유전완화전류와 누설전류를 분리해내어 박막의 측정온도 변화, 전계의 크기, 인가방향 변화, 후속 열처리에 따른 BST 박막의 전기전도 기구를 분석하였다. 그 결과, 유전완화전류는 Hoppiong process에 의한 BST박막내부의 trap된 전자들의 이동에 의한 전하재배치로 설명되어지며, 누설전류도 박막내의 trap에 의한 poole-Frenkel process에 의한 것임을 알 수 있었다. 그리고 각 전류성분에 기억하고 있는 trap이 BST박막내의 산호 결핍임을 추정하였다.