• Journal of Computing Science and Engineering
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• v.11 no.1
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• pp.9-23
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• 2017

NuDE 2.0 (Nuclear Development Environment 2.0) is a formal-method-based software development, verification and safety analysis environment for safety-critical digital I&Cs implemented with programmable logic controller (PLC) and field-programmable gate array (FPGA). It simultaneously develops PLC/FPGA software implementations from one requirement/design specification and also helps most of the development, verification, and safety analysis to be performed mechanically and in sequence. The NuDE 2.0 now consists of 25 CASE tools and also includes an in-depth solution for indirect commercial off-the-shelf (COTS) software dedication of new FPGA-based digital I&Cs. We expect that the NuDE 2.0 will be widely used as a means of diversifying software design/implementation and model-based software development methodology.

• Nuclear Engineering and Technology
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• v.53 no.4
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• pp.1167-1175
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• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• Journal of Sensor Science and Technology
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• v.7 no.5
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• pp.364-371
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• 1998

A novel antifuse has been developed for field programmable gate arrays (FPGA's) as a voltage programmable link with Al/$BaTiO_3/SiO_2$/TiW-silicide. The proper program voltage can be obtained by adjusting the deposition thickness of $BaTiO_3$ film. When a negative voltage was applied at bottom TiW-silicide electrode of the antifuse, based on $BaTiO_3(120{\AA})$/$SiO_2(120{\AA})$, the program voltage was about l4.4V and on-resistances were ranged between 40 and $50{\Omega}$. The current-voltage characteristics of antifuses are consistent with a Frenkel-Poole conduction model. However, there are some deviations depending on bias polarity that are probably due to the difference in the interface properties between Al/$BaTiO_3$ and TiW-silicide/$SiO_2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.424-434
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• 2015

Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.561-562
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• 2011

인 휠 모터를 이용하여 구동되는 전기차량은 각 모터의 동기 제어가 요구된다. 기존의 마이크로컨트롤러는 구동시킬 수 있는 모터의 개수가 제한되어 인 휠 모터를 이용하여 구동되는 전기차량과 같은 다축 제어 시스템에 적용하기가 어렵다. 따라서 본 논문에서는 FPGA(Field Programmable Gate Array)를 이용하여 4축 동기 SVPWM 기법을 구현하였으며, 시뮬레이션을 통하여 성능을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.

• Journal of Power Electronics
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• v.10 no.1
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• pp.65-71
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• 2010

This paper presents the design and implementation of voltage source inverter type SVPWM based speed control of an induction motor using a fuzzy PI controller. This scheme enables us to adjust the speed of the motor by controlling the frequency and amplitude of the stator voltage; the ratio of the stator voltage to the frequency should be kept constant. A model of the fuzzy control system is implemented in real time with a Xilinx FPGA XC3S 400E. It is introduced to maintain a constant speed to when the load varies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.379-388
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• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.85-92
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• 1995

A new partitioning algorithm has been developed to implement a large circuit by using multiple field programmable gate array (FPGA) chips. While the conventional partitioning is to minimze the number of nets cut under size constraints, partitioning for multiple FPGAs has several additional constraints so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two steps whhich are the intial partitioning for global optimization and the iterative partitioning improvements for constraint satisfaction. Experismental results using the MCNC benchmark examples show that our partition method produces better results thatn those of other recent approaches on the average.