• Title/Summary/Keyword: Field-effect mobility

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Operation characteristics of IGZO thin-film transistors (IGZO 박막트랜지스터의 동작특성)

  • Lee, Ho-Nyeon;Kim, Hyung-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.5
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    • pp.1592-1596
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    • 2010
  • According to the increase of the channel length with fixed width/length, characteristic curves of drain current as a function of gate bias voltage of indium gallium zinc oxide (IGZO) thin-film transistors moved to a positive direction of gate voltage, and field-effect mobility decreased. In case of fixed length and width of channel, field-effect mobility was lower and subthreshold slope was larger when drain bias voltage was higher. Due to large work function of IGZO, band bending at the junction region between IGZO channel and source/drain electrodes was expected to be in opposite direction to that between silicon and metal electrodes; this could explain the above results.

Anneal Temperature Effects on Hydrogenated Thin Film Silicon for TFT Applications

  • Ahn, Byeong-Jae;Kim, Do-Young;Yoo, Jin-Su;Junsin Yi
    • Transactions on Electrical and Electronic Materials
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    • v.1 no.2
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    • pp.7-11
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    • 2000
  • a-Si:H and poly-Si TFT(thin film transistor) characteristics were investigated using an inverted staggered type TFT. The TFT an as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. The poly-Si films were achieved by using an isothermal and RTA treatment for glow discharge deposited a-Si:H films. The a-Si:H films were cystallized at the various temperature from 600$^{\circ}C$ to 1000$^{\circ}C$. As anneal temperature was elevated, the TFT exhibited increased g$\sub$m/ and reduced V$\sub$ds/. V$\sub$T/. The poly-Si grain boundary passivation with grain boundary trap types and activation energies as a function of anneal temperature. The poly-si TFT showed an improved I$\sub$nm//I$\sub$off/ ratio of 10$\^$6/, reduced gate threshold voltage, and increased field effect mobility by three orders.

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Highly Crystalline 2,6,9,10-Tetrakis((4-hexylphenyl)ethynyl)anthracene for Efficient Solution-Processed Field-effect Transistors

  • Hur, Jung-A;Shin, Ji-Cheol;Lee, Tae-Wan;Kim, Kyung-Hwan;Cho, Min-Ju;Choi, Dong-Hoon
    • Bulletin of the Korean Chemical Society
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    • v.33 no.5
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    • pp.1653-1658
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    • 2012
  • A new anthracene-containing conjugated molecule was synthesized through the Sonogashira coupling and reduction reactions. 1-Ethynyl-4-hexylbenzene was coupled to 2,6-bis((4-hexylphenyl) ethynyl)anthracene-9,10-dione through a reduction reaction to generate 2,6,9,10-tetrakis((4-hexylphenyl)ethynyl) anthracene. The semiconducting properties were evaluated in an organic thin film transistor (OTFT) and a single-crystal field-effect transistor (SC-FET). The OTFT showed a mobility of around 0.13 $cm^2\;V^{-1}\;s^{-1}$ ($I_{ON}/I_{OFF}$ > $10^6$), whereas the SC-FET showed a mobility of 1.00-1.35 $cm^2\;V^{-1}\;s^{-1}$, which is much higher than that of the OTFT. Owing to the high photoluminescence quantum yield of 2,6,9,10-tetrakis((4-hexylphenyl)ethynyl) anthracene, we could observe a significant increase in drain current under irradiation with visible light (${\lambda}$ = 538 nm, 12.5 ${\mu}W/cm^2$).

Electrical Characteristics of Pentacene Thin Film Transistors.

  • Kim, Dae-Yop;Lee, Jae-Hyuk;Kang, Dou-Youl;Choi, Jong-Sun;Kim, Young-Kwan;Shin, Dong-Myung
    • 한국정보디스플레이학회:학술대회논문집
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    • 2000.01a
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    • pp.69-70
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    • 2000
  • There are currently considerable interest in the applications of conjugated polymers, oligomers, and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field-effect transistors and light-emitting diodes. In this study, pentacene thin-film transistors (TFTs) were fabricated on glass substrate. Aluminums were used for gate electrodes. Silicon dioxide was deposited as a gate insulator by PECVD and patterned by reactive ion etching (R.I.E). Gold was used for the electrodes of source and drain. The active semiconductor pentacene layer was thermally evaporated in vacuum at a pressure of about $10^{-8}$ Torr and a deposition rate $0.3{\AA}/s$. The fabricated devices exhibited the field-effect mobility as large as 0.07 $cm^2/V.s$ and on/off current ratio as larger than $10^7$.

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Spray coating of electrochemically exfoliated graphene/conducting polymer hybrid electrode for organic field effect transistor

  • Kim, Youn;Kwon, Yeon Ju;Hong, Jin-Yong;Park, Minwoo;Lee, Cheol Jin;Lee, Jea Uk
    • Journal of Industrial and Engineering Chemistry
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    • v.68
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    • pp.399-405
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    • 2018
  • We report the fabrication of organic field-effect transistors (OFETs) via spray coating of electrochemically exfoliated graphene (EEG) and conducting polymer hybrid as electrodes. To reduce the roughness and sheet resistance of the EEG electrodes, subsequent coating of conducting polymer (poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS)) and acid treatment was performed. After that, active channel layer was developed by spin coating of semiconducting poly(3-hexylthiophene) on the hybrid electrodes to define the bottom gate bottom contact configuration. The OFET devices with the EEG/PEDOT:PSS hybrid electrodes showed a reasonable electrical performances (field effect mobility = $0.15cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^2$, and threshold voltage = -1.57V). Furthermore, the flexible OFET devices based on the Polydimethlsiloxane (PDMS) substrate and ion gel dielectric layer exhibited higher electrical performances (field effect mobility = $6.32cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^3$, and threshold voltage = -1.06V) and excellent electrical stability until 1000 cycles of bending test, which means that the hybrid electrode is applicable to various organic electronic devices, such as flexible OFETs, supercapacitors, organic sensors, and actuators.

On the Method of Measuring the Mobility using the Microwave by the Hall Effect in the semiconductor (마이크로파를 이용하여 반도체내의 Hall에 의한 이동도측정방법)

  • 허영남
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.8 no.2
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    • pp.54-62
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    • 1983
  • The electric characteristics of semiconductor materials can be found by way of various methods, of which the measurement of the carrier mobility is thought to be of great importance. There exist some mobilty measurements, but the measurement based on Hall effect is the most widely uesd. In this paper is adopted the mobility measurement of semiconductor by the use of cylindrical eavity operated in the same shape as TE modes. It is hoped that the resultant values of measurement, the structure of measurement circut, cavity design and the raising of relevant problems may give much help to those who may interested in this field.

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Analysis of electron mobility in LDD region of NMOSFET (NMOSFET에서 LDD 영역의 전자 이동도 해석)

  • 이상기;황현상;안재경;정주영;어영선;권오경;이창효
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.10
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    • pp.123-129
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    • 1996
  • LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

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Thin Film Transistor Characteristics with ZnO Channel Grown by RF Magnetron Sputtering (RF Magnetron Sputtering으로 증착된 ZnO의 증착 특성과 이를 이용한 Thin Film Transistor특성)

  • Kim, Young-Woong;Choi, Duck-Kyun
    • Journal of the Microelectronics and Packaging Society
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    • v.14 no.3
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    • pp.15-20
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    • 2007
  • Low temperature processed ZnO-TFTs on glass below $270^{\circ}C$ for plastic substrate applications were fabricated and their electrical properties were investigated. Films in ZnO-TFTs with bottom gate configuration were made by RF magnetron sputtering system except for $SiO_2$ gate oxide deposited by ICP-CVD. ZnO channel films were grown on glass with various Ar and $O_2$ flow ratios. All of the fabricated ZnO-TFTs showed perfectly the enhancement mode operation, a high optical transmittance of above 80% in visible ranges of the spectrum. In the ZnO-TFTs with pure Ar process, the field effect mobility, threshold voltage, and on/off ratio were measured to be $1.2\;cm^2/Vs$, 8.5 V, and $5{\times}10^5$, respectively. These characteristic values are much higher than those of the ZnO-TFTs of which ZnO channel layers were processed with additional $O_2$ gas. In addition, ZnO-TFT with pure Af process showed smaller swing voltage of 1.86v/decade compared to those with $Ar+O_2$ process.

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Electrical Characteristics of SiC MOSFET Utilizing Gate Oxide Formed by Si Deposition (Si 증착 이후 형성된 게이트 산화막을 이용한 SiC MOSFET의 전기적 특성)

  • Young-Hun Cho;Ye-Hwan Kang;Chang-Jun Park;Ji-Hyun Kim;Geon-Hee Lee;Sang-Mo Koo
    • Journal of IKEEE
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    • v.28 no.1
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    • pp.46-52
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    • 2024
  • In this study, we investigated the electrical characteristics of SiC MOSFETs by depositing Si and oxidizing it to form the gate oxide layer. A thin Si layer was deposited approximately 20 nm thick on top of the SiC epi layer, followed by oxidation to form a gate oxide layer of around 55 nm. We compared devices with gate oxide layers produced by oxidizing SiC in terms of interface trap density, on-resistance, and field-effect mobility. The fabricated devices achieved improved interface trap density (~8.18 × 1011 eV-1cm-2), field-effect mobility (27.7 cm2/V·s), and on-resistance (12.9 mΩ·cm2).

Effects of thickness of GIZO active layer on device performance in oxide thin-film-transistors

  • Woo, C.H.;Jang, G.J.;Kim, Y.H.;Kong, B.H.;Cho, H.K.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.137-137
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    • 2009
  • Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.

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