• Journal of Korea Society of Digital Industry and Information Management
• /
• v.9 no.1
• /
• pp.129-139
• /
• 2013

In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of $16{\times}16$ size, and it takes about 4 sec for generating a hologram of a $1,024{\times}1,024$ size, using 6K point sources.

• Bulletin of the Korean Space Science Society
• /
• 2004.10b
• /
• pp.293-295
• /
• 2004

The Engineering Model of on-board computer was developed and tested completely with other sub-systems for STSAT-2. We designed the on-board computer of STSAT-2 which has some improved features compared with that of STSAT-l. A remarkable change is that the on-board computer has a structure of centeralized network communication without a Network Controller of the STSAT-l. That is, the on-board computer directly manages a satellite network. In addition, as many logics are implemented by Field Programmable Gate Array, so we can reduce the weight and size of on-board computer. Also, the developed on-board computer has more improved tolerance against Single Event Upsets and faults than that of the STSAT-l.

• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.70-73
• /
• 2004

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.533-536
• /
• 2000

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.445-446
• /
• 2006

This paper is concerned with a substantial speed up of image processing methods and less power consumption on 2D images making use of modern FPGA (Field Programmable Gate Array) technology. We implemented 2D FFT and edge detection algorithms based on FPGA and examined processing time and power consumption compared with C/C++ and Alti-Vec technologies.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.2
• /
• pp.83-88
• /
• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• Journal of Power Electronics
• /
• v.14 no.5
• /
• pp.937-945
• /
• 2014

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.

• Journal of Power Electronics
• /
• v.13 no.1
• /
• pp.104-112
• /
• 2013

This paper presents a comparative evaluation of various topologies for three-phase power converters using the hardware-in-the-loop (HIL) simulation technique. Various switch-mode AC-DC power converters are studied, and their performance with respect to total harmonic distortion (THD), efficiency, power factor and losses are analyzed. The HIL-simulation is implemented in an Altera Cyclone II DE2 Field Programmable Gate Array (FPGA) Board and in the Matlab/Simulink environment. A comparison of the simulation and HIL-simulation results is also provided.

• Advances in robotics research
• /
• v.2 no.1
• /
• pp.99-112
• /
• 2018

The main contribution of this work is the design of a field programmable gate array (FPGA) based ARX-Laguerre proportional-integral observation (PIO) system for fault detection and identification (FDI) in a multi-input, multi-output (MIMO) nonlinear uncertain dynamical robot manipulators. An ARX-Laguerre method was used in this study to dynamic modeling the robot manipulator in the presence of uncertainty and disturbance. To address the challenges of robustness, fault detection, isolation, and estimation the proposed FPGA-based PI observer was applied to the ARX-Laguerre robot model. The effectiveness and accuracy of FPGA based ARX-Laguerre PIO was tested by first three degrees of the freedom PUMA robot manipulator, yielding 6.3%, 10.73%, and 4.23%, average performance improvement for three types of faults (e.g., actuator fault, sensor faults, and composite fault), respectively.

• Proceedings of the IEEK Conference
• /
• 2007.07a
• /
• pp.223-224
• /
• 2007

To develop nuclear measurement system with characteristics including both re-configuration and multi-functions, we proposed a field programmable gate array (FPGA) technique to implement TDC which is more suitable for high energy Physics system. In TDC scheme, the timing resolution is more important than the count rates of channel. In order to manage pico-second resolution TDC, we used the delay components of FPGA, utilized the place and route (P&R) delay difference, and then got two ring oscillators. By setting P&R area constraints, we generated two precise ring oscillators with slightly different frequencies. Finally, we evaluated that the period difference of these two ring oscillators was about 60 pico-seconds, timing resolution of TDC.