• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• Nuclear Engineering and Technology
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• v.55 no.4
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• pp.1332-1341
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• 2023

Beam position measurement system can not only provide the beam position monitoring, but also be used for global orbit correction to reduce beam loss risk and maximize acceptance. The Beam Position Monitors (BPM) are installed along the synchrotron to acquire beam position with the front-end electronics and data acquisition system (DAQ). To realize high precision orbit measurement in the main heavy ion synchrotron and cooling storage ring of heavy-ion research facility in Lanzhou (HIRFL-CSRm), a series of alignment and calibration work has been implemented on the BPM and its DAQ system. This paper analyzed the tests performed in the laboratory as well as with beam based on the developed algorithms and hardware. Several filtering algorithms were designed and implemented on the acquired BPM raw data, then the beam position and resolution were calculated and analyzed. The results show that the position precision was significantly improved from more than 100 ㎛ to about 50 ㎛ by implementing the new designed filtering algorithm. According to the analyzation of the measurement results and upcoming physical requirements, further upgrade scheme for the BPM DAQ system of CSRm based on field programmable gate array (FPGA) technology was proposed and discussed.

• Journal of IKEEE
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• v.27 no.4
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• pp.601-609
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• 2023

In this paper, we propose an artificial intelligence-based high-speed fault diagnosis method using an FPGA in the event of a ground fault in a DC system. When applying artificial intelligence algorithms to fault diagnosis, a substantial amount of computation and real-time data processing are required. By employing an FPGA with AI-based high-speed fault diagnosis, the DC breaker can operate more rapidly, thereby reducing the breaking capacity of the DC breaker. therefore, in this paper, an intelligent high-speed diagnosis algorithm was implemented by collecting fault data through fault simulation of a DC system using Matlab/Simulink. Subsequently, the proposed intelligent high-speed fault diagnosis algorithm was applied to the FPGA, and performance verification was conducted.

• Nuclear Engineering and Technology
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• v.55 no.10
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• pp.3822-3830
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• 2023

The large-area Compton camera (LACC), featuring significantly high detection sensitivity, was developed for high-speed localization of gamma-ray sources. Due to the high gamma-ray interaction event rate induced by the high sensitivity, however, the multiplexer-based data acquisition system (DAQ) rapidly saturated, leading to deteriorated energy and imaging resolution at event rates higher than 4.7 × 10³ s^-1. In the present study, a new simultaneous multi-channel DAQ was developed to improve the energy and imaging resolution of the LACC even under high event rate conditions (10⁴-10⁶ s^-1). The performance of the DAQ was evaluated with several point sources under different event rate conditions. The results indicated that the new DAQ offers significantly better performance than the existing DAQ over the entire energy and event rate ranges. Especially, the new DAQ showed high energy resolution under very high event rate conditions, i.e., 6.9% and 8.6% (for 662 keV) at 1.3 × 10⁵ and 1.2 × 10⁶ s^-1, respectively. Furthermore, the new DAQ successfully acquired Compton images under those event rates, i.e., imaging resolutions of 13.8° and 19.3° at 8.7 × 10⁴ and 10⁶ s^-1, which correspond to 1.8 and 73 μSv/hr or about 18 and 730 times the background level, respectively.

• Journal of Advanced Navigation Technology
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• v.26 no.6
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• pp.441-447
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• 2022

In this paper, we propose a FLL-assisted-PLL based time synchronization algorithm for telemetry systems where frequency and phase errors exist in time synchronization pulse. The telemetry system may analyze the flight state by acquiring the state information in the distributed system. Therefor, in order to collect each state information without errors, precise time synchronization between the master and the slave is required. At this time, the master's time pulse have frequency and phase changes that can be caused by external and internal factors, so a method to maintain precision time synchronization is essential to provide telemetry data continuously. We propose the FLL-assisted-PLL based algorithm that is capable of high-speed synchronization and has high time synchronization accuracy. The proposed algorithm is verified through python simulation, and the VHDL Logic has been implemented in FPGA to check the performance according to the frequency errors and phase errors.

• Nuclear Engineering and Technology
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• v.56 no.1
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• pp.216-221
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• 2024

Ion cyclotron range of frequency (ICRF) heating system is an important auxiliary heating method in the experimental Advanced Superconducting Tokamak (EAST). In EAST, several megawatts of power are transmitted with coaxial transmission lines and coupled to the plasma. For the long pulse and high power operation of the ICRF waves heating system, it is very important to effectively control the power and initial phase of the ICRF signals. In this paper, a power and phase feedback control system is described based on field programmable gate array (FPGA) devices, which can realize complicated algorithms with the advantages of fast running and high reliability. The transmitted power and antenna phase are measured by a power and phase detector and digitized. The power and phase feedback control algorithms is designed to achieve the target power and antenna phase. The power feedback control system was tested on a dummy load and during plasma experiments. Test results confirm that the feedback control system can precisely control ICRF power and antenna phase and is robust during plasma variations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1061-1068
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• 2017

A RVDT is a sensor that measures angular displacement and the output signal of RVDT is a DSBSC-AM signal. For this reason, a DSBSC-AM demodulation processor is required to determine the angular displacement from the output signal. In this paper, DADC(Digital Angle to DC) which extracts the angular displacement from the output signal of a RVDT is implemented based-on modified Costas Loop usually used in the demodulation of DSBSC-AM signal by using FPGA. DADC can used with both 4-wire and 5-wire RVDTs and can exactly compensate the phase difference between the input excitation and output signals of a RVDT unlike the conventional analog RVDT signal conditioners which require external components. Since digital signal processing technique that can enhance the linearity is exploited, DADC shows 0.035% linearity error, which is smaller than 0.005% that of a conventional analog signal conditioner. The DADC are tested in an integrated experimental environment which includes a commercial RVDT sensor, ADC and an analog output block.

• Journal of KIISE
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• v.44 no.9
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• pp.932-945
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• 2017

In this paper, a new hardware and software architecture for a stereo vision processing system including rectification, disparity estimation, and visualization was developed. The developed method, named LArge scale stereo matching method using Support Point Interpolation (LASPI), shows excellence in real-time processing for obtaining dense disparity maps from high quality image regions that contain high density support points. In the real-time processing of high definition (HD) images, LASPI does not degrade the quality level of disparity maps compared to existing stereo-matching methods such as Efficient LArge-scale Stereo matching (ELAS). LASPI has been designed to meet a high frame-rate, accurate distance resolution performance, and a low resource usage even in a limited resource environment. These characteristics enable LASPI to be deployed to safety-critical applications such as an obstacle recognition system and distance detection system for autonomous vehicles. A Field Programmable Gate Array (FPGA) for the LASPI algorithm has been implemented in order to support parallel processing and 4-stage pipelining. From various experiments, it was verified that the developed FPGA system (Xilinx Virtex-7 FPGA, 148.5MHz Clock) is capable of processing 30 HD ($1280{\times}720pixels$) frames per second in real-time while it generates disparity maps that are applicable to real vehicles.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.