• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.41-50
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• 2014

In this paper, we proposed an error detection in Gaussian normal basis multiplier over $GF(2^n)$. It is shown that by using parity prediction, error detection can be very simply constructed in hardware. The hardware overheads are only one AND gate, n+1 XOR gates, and one 1-bit register in serial multipliers, and so n AND gates, 2n-1 XOR gates in parallel multipliers. This method are detect in odd number of bit fault in C = AB.

• Journal of the Korean School Mathematics Society
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• v.6 no.2
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• pp.87-99
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• 2003

As the development of computer science discrete mathematics has been developed accordingly. Discrete mathematics is one of the vital element for the development of the computer and IT technologies since it is the theoretical basis for these field of technologies. Currently, according the Seventh Curriculum Standards in Mathematics, high school students may participate in the class of discrete mathematics as one of their optional curriculum. However, discrete mathematics is a new to the most students in high school. Therefore, the teaching methods for the class of discrete mathematics must be carefully designed so that students acknowledge the importance of this new subject. For this purpose, we first show that why the algorithm is needed and then analyze the problem involved in the method of the traditional matrix multiplications. Finally, we suggest two matrix multiplication algorithms which are more efficient than the traditional method.

• Journal of Plant Biotechnology
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• v.8 no.1
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• pp.37-41
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• 2006

In vitro mass multiplication of Vanilla planifolia was investigated using node as explant. Multiple shoots were developed in MS medium supplemented with $2.0mgl^{-1}$ 6-benzylaminopurine and $1.0mgl^{-1}$ $\alpha$-naphthalene acetic acid. Multiple shoots were maintained for 6-T weeks with regular subculturing at the end of $3^{rd}$ week onto fresh medium. The maximum number of shoots at the rate of 12.8 per node segment was achieved over a period of four weeks. The elongated shoots were separated from the shoot clusters and were transferred onto half strength MS medium supplemented with indole-3-acetic acid ($1.0mgl^{-1}$) over a period of 28 days for induction of roots. The development of roots was observed on $7^{th}$ day of incubation. The in vitro raised plantlets were transferred to poly-cups, covered with polyethylene sheets and maintained under shade net for 25 days for hardening. Finally these plants were transferred to field and recorded that 85 % of tissue cultured plants were survived. From the present study, a simple and efficient micropropagation protocol was developed for Vanilla planifolia using single node segments as explants.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1120-1127
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• 2006

[ $GF(2^m)$ ] for elliptic curve cryptosystem. The proposed multiplier uses Gaussian normal basis representation and produces multiplication results at a rate of one per [m/w] clock cycles, where w is the selected we.4 size. We implement the p.oposed design using Xilinx XC2V1000 FPGA device. Our design has significantly less critical path delay compared with previously proposed hard ware implementations.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.35-41
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• 2000

In this paper, the multiplicative algorithm of two polynomals over finite field GF(2$^{m}$ ) is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. This multiplier is consisted of three operation unit: multiplicative operation unit, the modular operation unit, the primitive irreducible operation unit. The multiplicative operation unit is composed of AND gate, X-OR gate and multiplexer. The modular operation unit is constructed by AND gate, X-OR gate. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and interconnection of the cells are regular, well-suited for VLSI realization.

• Journal of Technologic Dentistry
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• v.24 no.1
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• pp.127-138
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• 2002

There are some cases that dental prosthesis does not operate as properly as expected in oral mouth. The reasons are such as a distortion of the mandibular, a fault of impression taking system or an extrusion of remaining teeth. One of dental prostheses to consider in the situations is the attachment which connects segment bridge. Active discussions are managed on theoretical side of this field but few on clinical side of it, which must be considered first. Accordingly I'd like to suggest a theoretical background for connect attachment of fixed segmented bridge. 1. As a bridge gets longer, burden on dental ligament is increased and the hardness of a bridge is lessened. 2. The flexibility of a bridge increases in ratio to 3 multiplication of the length and decreases in ratio to 3 multiplication of the width of occlusal surface and base of pontic. 3. Precision rest is needed to cope with the shake of teeth and the difference of axis direction among abutments. 4. Female part of the precision rest should be on middle abutment distal and male one on mesial of pontic. 5. Segmented attachment can be efficiently used to cope with long span bridgework and also in case that one piece casting can't be done because of slant of abutment.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.41-46
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• 2013

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Recently, many semi-systolic architectures have been proposed for multiplications over finite fields. Also, Montgomery multiplication algorithm is well known as an efficient arithmetic algorithm. In this paper, we induce an efficient multiplication algorithm and propose an efficient semi-systolic Montgomery multiplier based on polynomial basis. We select an ideal Montgomery factor which is suitable for parallel computation, so our architecture is divided into two parts which can be computed simultaneously. In analysis, our architecture reduces 30%~50% of time complexity compared to typical architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.140-148
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• 2008

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF($2^m$) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.1
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• pp.41-47
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• 2008

This paper presents a new digit level LSB-first multiplier for computing a modular multiplication and a modular squaring simultaneously over finite field GF($2^m$). To derive $L{\times}L$ digit level architecture when digit size is set to L, the previous algorithm is used and index transformation and merging the cell of the architecture are proposed. The proposed architecture can be utilized for the basic architecture for the crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity, and concurrency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.