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http://dx.doi.org/10.9723/jksiis.2013.18.2.041

Design of Montgomery Algorithm and Hardware Architecture over Finite Fields  

Kim, Kee-Won (단국대학교 소프트웨어학과)
Jeon, Jun-Cheol (금오공과대학교 컴퓨터공학과)
Publication Information
Journal of Korea Society of Industrial Information Systems / v.18, no.2, 2013 , pp. 41-46 More about this Journal
Abstract
Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Recently, many semi-systolic architectures have been proposed for multiplications over finite fields. Also, Montgomery multiplication algorithm is well known as an efficient arithmetic algorithm. In this paper, we induce an efficient multiplication algorithm and propose an efficient semi-systolic Montgomery multiplier based on polynomial basis. We select an ideal Montgomery factor which is suitable for parallel computation, so our architecture is divided into two parts which can be computed simultaneously. In analysis, our architecture reduces 30%~50% of time complexity compared to typical architectures.
Keywords
finite fields; semi-systolic architecture; Montgomery algorithm;
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Times Cited By KSCI : 2  (Citation Analysis)
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