• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.96-97
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• 2017

본 논문은 Gallium Nitride-Field Effect Transistor(GaN-FET)를 적용한 고방열 및 고전력밀도 모듈형 벅 컨버터를 제안한다. Si-MOSFET를 적용한 벅 컨버터는 높은 스위칭 손실로 인해 고주파수 구동 및 자기소자 사이즈 저감에 한계가 존재하여 고전력밀도화가 어렵다. 반면, 제안된 방식은 스위칭 특성이 우수한 GaN-FET를 적용하여 고주파수 구동이 가능하며, 추가로 평면형 인덕터를 적용함으로써 자기소자의 부피 저감을 통해 컨버터의 고전력밀도화 및 모듈화가 가능하다. 특히, 방열 플레이트 및 케이스로 구성된 새로운 고방열 구조를 통해 방열효과를 극대화 시킬 수 있다. 제안된 모듈형 벅 컨버터의 타당성 검증을 위해 입력전압 48V, 출력전압 24V의 300W급 시작품 제작을 통한 실험결과를 제시한다.

• Journal of Convergence for Information Technology
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• v.11 no.11
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• pp.159-165
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• 2021

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.

• Journal of IKEEE
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• v.19 no.4
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• pp.514-519
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• 2015

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.398-403
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• 2017

본 연구에서는 gate-all-around(GAA) 수직 나노선 Field-Effect Transistor(FET)의 소스/드레인 반도체/실리사이드 접합에 존재하는 Schottky 장벽이 트랜지스터의 DC특성에 미치는 영향에 대하여 조사하였다. Non-Equilibrium Green's Function와 Poisson 방정식 기반의 시뮬레이터를 사용하여, Schottky 장벽의 위치와 높이, 그리고 채널 단면적의 크기에 따른 전류-전압 특성 곡선과 에너지 밴드 다이어그램을 통해 분석을 수행하였다. 그 결과, 드레인 단의 Schottky 장벽은 드레인 전압에 의해 장벽의 높이가 낮아져 전류에 주는 영향이 작지만, 소스 단의 Schottky 장벽은 드레인 전압과 게이트 전압으로 제어가 불가능하여 외부에서 소스 단으로 들어오는 캐리어의 이동을 방해하여 큰 DC성능 저하를 일으킨다. 채널 단면적 크기에 따른 DC특성 분석 결과로는 동작상태의 전류밀도는 채널의 폭이 5 nm 일 때까지는 유지되고, 2 nm가 되면 그 크기가 매우 작아지지만, 채널 단면적은 Schottky 장벽에 영향을 끼치지 못하였다. 본 논문의 분석 결과로 향후 7 nm technology node 에 적용될 GAA 수직 나노선 FET의 소자 구조 설계에 도움이 되고자 한다.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.260-263
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• 2013

A semiconducting single-walled carbon nanotube (SWCNT) field-effect transistor (FET) in a top-gate model was constructed. The effect of different high-${\kappa}$ dielectric materials ($Al_2O_3$, $HfO_2$ and HfSiON) and various temperatures with a wide range from 50K to 500K on the performance of such nominal device were investigated. Several key device parameters including the on/off ratio of the current, transconductance ($g_m$), subthreshold swing, and carrier mobility were used to evaluate the device performance. The simulated results fit well with the experiment results previously published.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.297-304
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• 2017

The purpose of this paper is to analyze losses because of switching devices and the secondary side circuit diodes of 500 W full bridge dc-dc converter by applying gallium nitride (GaN) field-effect transistor (FET), which is one of the wide band gap devices. For the detailed device analysis, we translate the specific resistance relation caused by the GaN FET material property into algebraic expression, and investigate the influence of the GaN FET structure and characteristic on efficiency and system specifications. In addition, we mathematically compare the diode rectifier circuit loss, which is a full bridge dc-dc converter secondary side circuit, with the synchronous rectifier circuit loss using silicon metal-oxide semiconductor (Si MOSFET) or GaN FET, which produce the full bridge dc-dc converter analytical value validity to derive the final efficiency and loss. We also design the heat sink based on the mathematically derived loss value, and suggest the heat sink size by purpose and the heat divergence degree through simulation.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.236-242
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• 2021

In this paper, we report the fabrication of the tip-on-gate of a field-effect-transistor (ToGoFET) probe using a standard complementary metal-oxide-semiconductor (CMOS) process and the performance evaluation of the fabricated probe. After the CMOS process, I-V characteristic measurement was performed on the reference MOSFET. We confirmed that the ToGoFET probe could be operated at a gate voltage of 0 V due to channel ion implantation. The transconductance at the operating point (Vg = 0 V, Vd = 2 V) was 360 ㎂/V. After the fabrication process was completed, calibration was performed using a pure metal sample. For sensitivity calibration, the relationship between the input voltage of the sample and the output current of the probe was determined and the result was consistent with the measurement result of the reference MOSFET. An oxide sample measurement was performed as an example of an application of the new ToGoFET probe. According to the measurement, the ToGoFET probe could spatially resolve a hundred nanometers with a height of a few nanometers in both the topographic image and the ToGoFET image.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.277.1-277.1
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• 2016

We report on synthesis of large-area MoS2 using chemical vapor deposition (CVD). Relatively uniform MoS2 are obtained. To fabricate field-effect transistor (FET) devices, MoS2 films are transferred to another SiO2/Si substrate using polystyrene (PS) and patterned using oxygen plasma. In addition, to reduce contact resistance, synthesis of graphene used as channel. Device characteristics are presented and compared with the reported results.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.358-365
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• 2016

We propose a novel application of random forest, a machine learning-based general classification algorithm, to analyze the influence of design attributes on the silicon-to-SPICE (S2S) gap. To improve modeling accuracy, we introduce magnification of learning data as well as randomization for the counting of design attributes to be used for each tree in the forest. From the automatically generated decision trees, we can extract the so-called importance and impact indices, which identify the most significant design attributes determining the S2S gap. We apply the proposed method to actual silicon data, and observe that the identified design attributes show a clear trend in the S2S gap. We finally unveil 10nm key fin-shaped field effect transistor (FinFET) structures that result in a large S2S gap using the measurement data from 10nm test vehicles specialized for model-hardware correlation.