• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.71-76
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• 2007

The effect of crosstalk errors is most significant in high-performance circuits. This paper presents effective test patterns for SoC and Board level interconnects considering actual effective aggressors. Initially '6n' algorithm, where 'n' is the total number of interconnect nets, is analyzed to detect and diagnose 100% crosstalk faults. Then, more efficient algorithm is proposed reducing the number of test patterns significantly while maintaining complete crosstalk fault coverage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1149-1159
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• 1998

This paper presents the Controllable Self-Checking(CSC) Checker at which can be used the Fault-Tolerant System with the redundancy. According to the critical level of output(of system), especially, it can be instructed the time if it has to check the output or not. We adop the deterministic test, performed on-line, to detect the faults with a minimal test set. The results show the Parity 2-rail checker(P-TRC) which is designed much simpler than the checker has the higher fault coverage than the existent checker.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.384-387
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• 1999

In this paper, we have proposed a testing methodology for Speed-Independent asynchronous control circuits using the self-checking property where the circuit detects certain classes of faults during normal operation. To exploit self-checking properties of Speed-Independent circuits, the Proposed methodology generates tests from the specification of the target circuit which describes the behavior of the circuit. The generated tests are applied to a fault-free and a faulty circuit, and target faults can be detected by the comparison of the outputs of the both circuits. For the purpose of efficient comparison, reachability information of the both circuits in the form of BDD's is used and operations are conducted by BDD manipulations. The identification for undetectable faults in testing is also used to increase efficiency of the proposed methodology. The proposed identification uses only topological information of the target circuit and reachability information of the good circuit which was generated in the course of preprocess. Experimental results show that high fault coverage is obtained for synthesized Speed-Independent circuits and the use of the identification process decreases the number of tests and execution time.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.43-49
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• 2011

A distance relay scheme is commonly used for backup protection. This scheme, called a step distance protection, is comprised of 3 steps for graded zones having different operating time. As for the conventional step distance protection scheme, Zone 2 can exceed the ordinary coverage excessively in case of a transformer protection relay especially. In this case, there can be overlapped protection area from a backup protection relay and, therefore, malfunctions can occur when any fault occurs in the overlapped protection area. Distance relays and overcurrent relays are used for backup protection generally, and both relays have normally this problem, the maloperation, caused by a fault in the overlapped protection area. Corresponding to an IEEE standard, this problem can be solved with the modification of the operating time. On the other hand, in Korea, zones are modified to cope with this problem in some specific conditions. These two methods may not be obvious to handle this problem correctly because these methods, modifying the common rules, can cause another coordination problem. To overcome this problem clearly, this paper describes an improved backup protection coordination scheme using an IEC 61850-based distance relay for transformer backup protection. IEC 61850-based IED(Intelligent Electronic Device) and the network system based on the kernel 2.6 LINUX are realized to verify the proposed method. And laboratory tests to estimate the communication time show that the proposed coordination method is reliable enough for the improved backup protection scheme.

• Journal of Information Processing Systems
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• v.13 no.5
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• pp.1089-1102
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• 2017

In software systems, it has been observed that a fault is often caused by an interaction between a small number of input parameters. Even for moderately sized software systems, exhaustive testing is practically impossible to achieve. This is either due to time or cost constraints. Combinatorial (t-way) testing provides a technique to select a subset of exhaustive test cases covering all of the t-way interactions, without much of a loss to the fault detection capability. In this paper, an approach is proposed to generate 2-way (pairwise) test sets using genetic algorithms. The performance of the algorithm is improved by creating an initial solution using the overlap coefficient (a similarity matrix). Two mutation strategies have also been modified to improve their efficiency. Furthermore, the mutation operator is improved by using a combination of three mutation strategies. A comparative survey of the techniques to generate t-way test sets using genetic algorithms was also conducted. It has been shown experimentally that the proposed approach generates faster results by achieving higher percentage coverage in a fewer number of generations. Additionally, the size of the mixed covering arrays was reduced in one of the six benchmark problems examined.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.5
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• pp.1829-1846
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• 2021

Transient faults occur in computation units of a processor, which can cause control flow errors (CFEs) and compromise system reliability. The software-based methods perform illegal control flow detection by inserting redundant instructions and monitoring signature. However, the existing methods not only have drawbacks in terms of performance overhead, but also lack of configurability. We propose a configurable approach CCFCA for detecting CFEs. The configurability of CCFCA is implemented by analyzing the criticality of each region and tuning the detecting granularity. For critical regions, program blocks are divided according to space-time overhead and reliability constraints, so that protection intensity can be configured flexibly. For other regions, signature detection algorithms are only used in the first basic block and last basic block. This helps to improve the fault-tolerant efficiency of the CCFCA. At the same time, CCFCA also has the function of solving confusion and instruction self-detection. Our experimental results show that CCFCA incurs only 10.61% performance overhead on average for several C benchmark program and the average undetected error rate is only 9.29%. CCFCA has high error coverage and low overhead compared with similar algorithms. This helps to meet different cost requirements and reliability requirements.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.44-53
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• 1999

Generating diagnostic test patterns for combinational circuits remain to be a very difficult problem. For example, ISCAS85 c7552 benchmark circuit has 100 million fault pairs, Thus, we need more sophisticated algorithm to get more information. A new diagnostic algorithm for test pattern generation is suggested and implemented in this paper. DIATEST algorithm based on PODEM is also implemented for comparison to the new algorithm. These two algorithms have been applied to ISCAS85 benchmark circuits. Experimental results show that (1) both algorithms achieve fault pair coverage over 99%, (2) total test length of the new algorithm is much shorter than that of DIATEST, and (3) the new algorithm gives much more information used for making diagnostic dictionary, diagnostic decision tree or diagnostic test system despite DIATEST is faster than the new algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.558-565
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• 2000

While research of ATPG(automatic test pattern generation) for combinational circuits almost reaches a satisfiable level, one for sequential circuits still requires more research. In this paper, we propose new algorithm for sequential ATPG based on state information learning. By efficiently storing the information of the state searched during the process of test pattern generation and using the state information that has been already stored, test pattern generation becomes more efficient in time, fault coverage, and the number of test patterns. Through some experiments with ISCAS '89 benchmark circuits, the efficiency of the proposed method is shown.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.189-192
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• 2000

In this paper, we propose the novel test method to detect short and open faults in CMOS Op-amp. The proposed method is composed of two test steps - the offset and the high frequency test. Using HSPICE simulation, we get a 100％ fault coverage. To verify the proposed method, we design and fabricate the CMOS op-amp that contains various short and open faults through Hyundai 0.65$\mu\textrm{m}$ 2-poly 2-metal CMOS process. Experimental results of fabricated chip demonstrate that the proposed test method can detect short and open faults in CMOS Op-amp.